Adaptive targeting of read levels in storage devices
View Patent ↗A storage device may include a controller and a plurality of memory devices logically divided into a plurality of pages. Each page in the plurality of pages may include a plurality of bits. The controller may be configured to: apply a read level to a control gate of a transistor for each respective bit in the plurality of bits; determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits; determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value; and adjust, based on the error ratio, the read level.
1. A storage device comprising:
a plurality of memory devices logically divided into a plurality of pages, each page of the plurality of pages including a respective plurality of bits; and
a controller configured to:
apply a read level to a control gate of a transistor for each respective bit in the plurality of bits;
determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits;
determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value;
responsive to determining that the error ratio satisfies a threshold ratio, determine whether the error ratio satisfies a limit ratio;
responsive to determining that the error ratio does not satisfy the limit ratio, adjust, based on the error ratio, the read level; and
responsive to determining that the error ratio satisfies the limit ratio, perform a read calibration.
2. The storage device of claim 1 , wherein an amount of current below a threshold current indicates the first bit value and an amount of current above the threshold current indicates the second bit value.
3. The storage device of claim 1 ,
wherein the threshold ratio is a first threshold ratio,
wherein the limit ratio is a first limit ratio, and
wherein the controller is configured to:
responsive to determining that the error ratio satisfies the first threshold ratio and does not satisfy the first limit ratio, adjust the read level by at least decreasing the read level; and
responsive to determining that the error ratio satisfies a second threshold ratio and does not satisfy a second limit ratio, increase the read level.
4. The storage device of claim 3 , wherein decreasing the read level includes decreasing the read level by a fixed amount, wherein increasing the read level includes increasing the read level by a fixed amount.
5. The device of claim 3 , wherein the first threshold ratio is inversely related to the second threshold ratio.
6. The device of claim 3 , wherein the first limit ratio is inversely related to the second limit ratio.
7. The storage device of claim 1 , wherein the read level is initialized to a predetermined value.
8. The storage device of claim 1 , wherein the controller is configured to determine the error ratio and update the read level in response to determining the respective value for each bit from the plurality of bits.
9. The device of claim 1 , wherein a magnitude of the adjustment in the read level is based on a magnitude of the error ratio.
10. The device of claim 1 , wherein the controller is configured to determine the error ratio when the device is in an idle state.
11. The device of claim 1 , wherein the threshold ratio is a number between a target ratio and the limit ratio, wherein the target ratio is a ratio that indicates the number of bits that are written as the first bit value but are incorrectly read as the second bit value is equal to the number of bits that are written as the second bit value but are incorrectly read as the first bit value.
12. A method comprising:
applying, by a controller of a storage device, a read level to a control gate of a transistor for each respective bit in a plurality of bits;
determining, by the controller and based on an amount of current that flows through the transistor, a respective value for each bit from the plurality of bits;
determining, by the controller and based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value;
responsive to determining that the error ratio satisfies a threshold ratio, determining, by the controller, whether the error ratio satisfies a limit ratio;
responsive to determining that the error ratio does not satisfy the limit ratio, adjusting, by the controller and based on the error ratio, the read level; and
responsive to determining that the error ratio satisfies the limit ratio, performing, by the controller, a read calibration.
13. The method of claim 12 , wherein determining a respective value for each bit in the plurality of bits includes comparing the amount of current to a threshold, wherein an amount of current below the threshold current indicates the first bit value and an amount of current above the threshold current indicates the second bit value.
14. The method of claim 12 ,
wherein the threshold ratio is a first threshold ratio,
wherein the limit ratio is a first limit ratio, and
wherein adjusting the read level includes:
responsive to determining that the error ratio satisfies the first threshold ratio and does not satisfy the first limit ratio, decrease, by the controller, the read level; and
responsive to determining that the error ratio satisfies a second threshold ratio and does not satisfy a second limit ratio, increasing, by the controller, the read level.
15. The method of claim 14 , wherein decreasing the read level includes decreasing the read level by a fixed amount, wherein increasing the read level includes increasing the read level by a fixed amount.
16. The method of claim 12 , further comprising initializing the read level to a predetermined value.
17. The method of claim 12 , further comprising determining the error ratio and updating the read level in response to determining the respective value for each bit from the plurality of bits.
18. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors of a storage device to:
apply a read level to a control gate of a transistor for each respective bit in the plurality of bits;
determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits;
determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value;
responsive to determining that the error ratio satisfies a threshold ratio, determine whether the error ratio satisfies a limit ratio;
responsive to determining that the error ratio does not satisfy the limit ratio, adjust, based on the error ratio, the read level; and
responsive to determining that the error ratio satisfies the limit ratio, perform a read calibration.
19. The non-transitory computer-readable storage medium of claim 18 , wherein the threshold ratio is a first threshold ratio, wherein the limit ratio is a first limit ratio, and wherein the non-transitory computer-readable storage medium further comprises instructions that, when executed, configure one or more processors of the storage device to:
responsive to determining that the error ratio satisfies the first threshold ratio and does not satisfy the first limit ratio, adjust the read level by at least decreasing the read level,
and
responsive to determining that the error ratio satisfies a second threshold ratio and does not satisfy a second limit ratio, increase the read level.
20. A system comprising:
means for applying a read level to a control gate of a transistor for each respective bit in a plurality of bits;
means for determining a respective value for each bit from the plurality of bits;
means for determining an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value;
responsive to determining that the error ratio satisfies a threshold ratio, means for determining whether the error ratio satisfies a limit ratio;
responsive to determining that the error ratio does not satisfy the limit ratio, means for adjusting the read level; and
responsive to determining that the error ratio satisfies the limit ratio, means for performing a read calibration.