Solid-state device with load isolation
View Patent ↗Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices.
1. A solid state drive system comprising:
a memory controller electrically coupled to a channel, wherein the memory controller is configured to select one of a plurality of flash memory devices and, in response to the selection, provide a control signal; and
a multiplexing circuit electrically coupled to the channel and configured to be coupled to the plurality of flash memory devices, wherein the multiplexing circuit is configured to receive the control signal from the memory controller and, in response, to couple the channel to the selected one of the plurality of flash memory devices and to decouple the remainder of the plurality of flash memory devices from the memory controller.
2. The solid state drive system of claim 1 , wherein the memory controller is configured to detect an exception condition and, in response, provide an output enable signal to the multiplexing circuit to decouple at least one of the plurality of flash memory devices from the memory controller.
3. The solid state drive system of claim 2 , wherein the exception condition includes a power supply disruption.
4. The solid state drive system of claim 3 , wherein the memory controller is configured to receive a signal from a power supply, the signal indicating a power supply disruption.
5. The solid state drive system of claim 2 , wherein the multiplexing circuit is configured to decouple the at least one of the plurality of flash memory devices from the memory controller by decoupling the multiplexing circuit from a power supply.
6. The solid state drive system of claim 1 , wherein the multiplexing circuit comprises a plurality of isolation devices arranged in a tree topology.
7. The solid state drive system of claim 6 , wherein at least one of the plurality of isolation devices comprises a field effect transistor switch.
8. The solid state drive system of claim 6 , wherein at least one of the plurality of isolation devices comprises an electrostatic discharge (ESD) protection circuit.
9. The solid state drive system of claim 1 , wherein the multiplexing circuit is configured to receive the control signal at one of: a rate of about 400 million transfers per second (MT/s), or at a rate between about 400 MT/s and about 1000 MT/s.
10. A flash memory system comprising:
a plurality of flash memory devices electrically coupled to a channel;
a multiplexing circuit electrically coupled to the channel and a port, which is configured to be coupled to a memory controller, wherein the multiplexing circuit is configured to receive a select signal from the memory controller and, in response, to couple one of the plurality of flash memory devices to the port and to decouple the remainder of the plurality of flash memory devices from the port.
11. The flash memory system of claim 10 , wherein the multiplexing circuit is configured to receive an output enable signal from the memory controller, wherein if the output enable signal is in a first state, the multiplexing circuit is configured to decouple each of the plurality of flash memory devices from the memory controller, and wherein if the output enable signal is in a second state, the multiplexing circuit is configured to couple at least one of the plurality of flash memory devices to the memory controller.
12. The flash memory system of claim 11 , wherein the multiplexing circuit is configured to decouple each of the plurality of flash memory devices from the memory controller by decoupling the multiplexing circuit from a power supply.
13. The flash memory system of claim 10 , wherein the multiplexing circuit comprises a plurality of isolation devices arranged in a tree topology.
14. The flash memory system of claim 13 , wherein the tree topology comprises a binary tree topology.
15. The flash memory system of claim 13 , wherein at least one of the plurality of isolation devices comprises a field effect transistor switch.
16. The flash memory system of claim 13 , wherein at least one of the plurality of isolation devices comprises an electrostatic discharge (ESD) protection circuit.
17. The flash memory system of claim 13 , wherein at least one of the plurality of isolation devices comprises a buffer.
18. The flash memory system of claim 10 , wherein the multiplexing circuit is configured to receive the control signal at one of: a rate of about 400 million transfers per second (MT/s), or at a rate between about 400 MT/s and about 1000 MT/s.
19. A method implemented in a solid state drive system comprising:
receiving a data control signal and a select command signal from a memory controller at an isolation device;
transmitting the data control signal from the isolation device to a first memory device when the select command signal is in a first selection state; and
transmitting the data control signal from the isolation device to a second memory device when the select command signal is in a second selection state.
20. The method of claim 19 , further comprising:
receiving an output enable signal from the memory controller at the isolation device;
if the output enable signal is at an output disable state,
decoupling the first memory device and the second memory device from the memory controller.