IP Library Granted Patent US 10,289,323
Granted Patent B2
US 10,289,323 · App. 16/017,950 · Granted May 14, 2019

Handling thermal shutdown for memory devices

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Quick Facts
Patent No.
US 10,289,323
App. No.
16/017,950
Granted
May 14, 2019
Kind
B2
Abstract

A memory device including a controller for handling thermal shutdown of the memory device. The control system acquires temperatures of a plurality of non-volatile memory elements in the memory device from one or more temperature detectors at a first frequency. Upon determining that the temperature of one of the plurality of non-volatile memory elements is above a threshold, the controller activates thermal throttling for the plurality of non-volatile memory elements and flushes metadata from a volatile memory element in the memory device to the plurality of non-volatile memory elements for future recovery of the memory device.

Claims (73)

1. A method, comprising:

upon experiencing a shutdown, powering up a memory device;

determining a state of a recovery flag in a boot block, wherein the recovery flag is set upon the memory device experiencing an abrupt shutdown;

scanning a log block to determine a last good page that was processed by the memory device;

determining a state of a graceful shutdown flag;

applying metadata stored in a control block for rebuilding data in a DRAM based on the recovery flag being set and the graceful shutdown flag being reset;

configuring the DRAM; and

enabling access to the memory device to continue read/write operations.

2. The method of claim 1 , further comprising regenerating new metadata in the DRAM based on the recovery flag being reset and the graceful shutdown flag being reset.

3. The method of claim 1 , further comprising generating metadata based on the graceful shutdown flag being set.

4. The method of claim 1 , wherein metadata stored in a control block includes one or more of XOR parity bins, CVD tables, and flash translation layer logical block address tables from previously-flushed metadata.

5. The method of claim 1 , wherein scanning a log block is performed by firmware in a controller associated with the memory device.

6. The method of claim 1 , wherein the graceful shutdown flag is set by completion of NAND die read/write operations.

7. The method of claim 1 , wherein rebuilding data in the DRAM includes checking, by a controller, the recovery flag and using a pointer in the recovery flag to access metadata stored in a control block.

8. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read/write operations;

a volatile memory element configured to store metadata of the memory device;

one or more temperature detectors configured to measure temperatures of the plurality of non-volatile memory elements;

a controller configured to:

acquire the temperatures of the plurality of non-volatile memory elements from the one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activate thermal throttling for the plurality of non-volatile memory elements; and

flush the metadata from the volatile memory element to the plurality of non-volatile memory elements; and

means for recovering metadata after an abrupt shutdown, comprising:

means for powering up the memory device upon experiencing a shutdown;

means for determining a state of a recovery flag in a boot block, wherein the recovery flag is set upon the memory device experiencing an abrupt shutdown;

means for scanning a log block to determine a last good page that was processed by the memory device;

means for determining a state of a graceful shutdown flag;

means for applying metadata stored in a control block for rebuilding data in a DRAM based on the recovery flag being set and the graceful shutdown flag being reset;

means for configuring the DRAM; and

means for enabling access to the memory device to continue read/write operations.

9. The memory device of claim 8 , wherein the memory device comprises a Solid State Drive (SSD).

10. The memory device of claim 8 , wherein each of the plurality of non-volatile memory elements comprises a NAND die.

11. The memory device of claim 8 , wherein the volatile memory element comprises a random-access memory.

12. The memory device of claim 8 , wherein the one or more temperature detectors are attached to the plurality of non-volatile memory elements.

13. The memory device of claim 8 , wherein the controller comprises a NAND controller.

14. A controller, comprising:

a processor;

a memory containing a program that, when executed on the processor, performs an operation, the operation comprising:

acquiring temperatures of a plurality of non-volatile memory elements in a memory device from one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activating thermal throttling for the plurality of non-volatile memory elements; and

flushing metadata of the memory device from a volatile memory element in the memory device to the plurality of non-volatile memory elements; and

means for recovering metadata after an abrupt shutdown, comprising:

means for powering up the memory device upon experiencing a shutdown;

means for determining a state of a recovery flag in a boot block, wherein the recovery flag is set upon the memory device experiencing an abrupt shutdown;

means for scanning a log block to determine a last good page that was processed by the memory device;

means for determining a state of a graceful shutdown flag;

means for applying metadata stored in a control block for rebuilding data in a DRAM based on the recovery flag being set and the graceful shutdown flag being reset;

means for configuring the DRAM; and

means for enabling access to the memory device to continue read/write operations.

15. The controller of claim 14 , wherein flushing metadata of the memory device comprises flushing the metadata from the volatile memory element to a plurality of control blocks in the plurality of non-volatile memory elements.

16. The controller of claim 14 , further configured to set a status flag indicating metadata is present in a plurality of control blocks.

17. The controller of claim 14 , further configured to set a status flag in a boot block in the plurality of non-volatile memory elements.

18. The controller of claim 14 , further configured to set a status flag after successfully flushing the metadata.

19. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read/write operations;

a volatile memory element configured to store metadata of the memory device;

a controller coupled to the plurality of non-volatile memory elements and coupled to the volatile memory element; and

means for recovering metadata after an abrupt shutdown, comprising:

means for powering up the memory device upon experiencing a shutdown;

means for determining a state of a recovery flag in a boot block, wherein the recovery flag is set upon the memory device experiencing an abrupt shutdown;

means for scanning a log block to determine a last good page that was processed by the memory device;

means for determining a state of a graceful shutdown flag;

means for applying metadata stored in a control block for rebuilding data in a DRAM based on the recovery flag being set and the graceful shutdown flag being reset;

means for configuring the DRAM; and

means for enabling access to the memory device to continue read/write operations.

20. The memory device of claim 19 , wherein the memory device comprises a Solid State Drive (SSD).

21. The memory device of claim 19 , wherein each of the plurality of non-volatile memory elements comprises a NAND die.

22. The memory device of claim 19 , wherein the volatile memory element comprises a random-access memory.

23. The memory device of claim 19 , wherein the recovery flag includes a pointer pointing to an address in volatile memory storing metadata flushed in a cycle immediately prior to the abrupt shutdown.

24. The memory device of claim 19 , wherein the controller comprises a NAND controller.

25. The memory device of claim 19 , further comprising means for regenerating new metadata in DRAM whenever the recovery flag is reset and the graceful shutdown flag is reset.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2019
From: YANG, NIAN NILES; KAMILA, VARUNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047935/0736 →