Methods for a random read and read/write block accessible memory
View Patent ↗In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
1. A method comprising:
mapping, with a controller, addresses of a disk-read-only-memory (disk-ROM) into a processor address space, the disk-ROM including a memory that is writeable with a disk-like write access and readable with both a disk-like read access and a random read access;
writing data into memory locations of the disk-ROM using a disk-like write access in response to the mapped addresses in the processor address space; and
reading data from the memory locations of the disk-ROM using a random read access in response to the mapped addresses in the processor address space.
2. The method of claim 1 , wherein
in response to a machine instruction the random read access reads an expected data granularity from the memory of the disk-ROM, and
the disk-like write access writes a block of data into the memory locations of the disk-ROM.
3. The method of claim 2 , further comprising:
reading data from the memory locations of the disk-ROM using a disk-like read access in response to the mapped addresses in the processor address space,
wherein the disk-like read access reads a block of data from the memory locations of the disk-ROM.
4. The method of claim 3 , wherein
the controller includes a read/write block access controller and a random read memory controller,
the read/write block access controller to control the disk-like write access and the disk-like read access to the memory locations of the disk-ROM, and
the random read memory controller to control the random read access to the memory locations of the disk-ROM.
5. The method of claim 2 , wherein
the expected data granularity for the random read access is less than a block size and a page size.
6. The method of claim 5 , wherein
the expected data granularity is set by a computer operating system or computer hardware.
7. The method of claim 6 , wherein
the expected data granularity is one byte.
8. The method of claim 6 , wherein
the expected data granularity is a half word.
9. The method of claim 6 , wherein
the expected data granularity is a word.
10. The method of claim 6 , wherein
the expected data granularity is a double word.
11. The method of claim 6 , wherein
the expected data granularity is a quad word.
12. The method of claim 1 , further comprising:
in response to the random read access, selectively forming a unidirectional data path from the disk-ROM to a bus; and
in response to the disk-like write access and the disk-like read access, selectively forming a bi-directional data path between the disk-ROM and the bus.
13. A method comprising:
mapping, with a controller, address locations of a memory array into processor address space, the memory array being block read/write accessible and random read memory accessible;
performing a block write access into the memory array to store a sequence of data in a respective first sequence of memory locations; and
performing a random read memory access into the memory array to read out data stored in one memory location of the respective first sequence of memory locations.
14. The method of claim 13 , further comprising:
performing a block read access into the memory array to read out a sequence of data stored in a second respective sequence of memory locations written by one or more prior block write accesses.
15. The method of claim 14 , wherein
the respective first sequence of data is a first data block and the block write access writes the first data block into the memory array;
the one memory location is a data byte in the first data block and the random read memory access reads the data byte out from the memory array; and
the respective second sequence of data is a second data block and the block read access reads out the second data block from the memory array.
16. The method of claim 14 , wherein
the controller includes a read/write block access controller and a random read memory controller,
the read/write block access controller to control the block write access and the block read access to the memory array, and
the random read memory controller to control the random read memory access to the memory array.
17. The method of claim 14 , further comprising:
in response to the random read memory access, selectively forming a unidirectional data path from the memory array to a bus; and
in response to the block write access and the block read access, selectively forming a bi-directional data path between the memory array and the bus.
18. A method in a system including a hard disk drive and a memory array, the method comprising:
mapping, with a controller, address locations of the memory array into processor address space, wherein the memory array is adapted to be read and written like a disk and read like a random access memory;
bypassing the hard disk drive to perform a block write access into the memory array to write a first sequence of data in a respective first sequence of memory locations in the memory array;
bypassing the hard disk drive to perform a block read access into the memory array to read out a second sequence of data in a respective second sequence of memory locations in the memory array; and
bypassing the hard disk drive and a main memory to perform a random read memory access from the memory array to read out data stored in one memory location of the respective first sequence of memory locations.
19. The method of claim 18 , wherein
the first sequence of data is a first data block and the block write access writes the first data block into the respective first sequence of memory locations in the memory array;
the second sequence of data is a second data block and the block read access reads out the second data block from the respective second sequence of memory locations in the memory array; and
the data stored in the one memory location is a data byte in the first data block and the random read memory access reads the data byte out from the one memory location of the respective first sequence of memory locations in the memory array.
20. The method of claim 18 , wherein
the controller includes a read/write block access controller and a random read memory controller,
the read/write block access controller to control the block write access and the block read access into the memory array, and
the random read memory controller to control the random read memory access into the memory array.
21. The method of claim 18 , further comprising:
in response to the random read memory access, selectively forming a unidirectional data path from the memory array to a bus; and
in response to the block write access and the block read access, selectively forming a bi-directional data path between the memory array and the bus.
22. A method comprising:
mapping, with a controller, address locations of a memory array into processor address space, wherein the memory array can be read and written like a hard disk and also read like a main memory of a processor complex;
performing a block write access into the memory array to write a first sequence of data into a first respective sequence of memory locations in the memory array;
performing a block read access into the memory array to read out a second sequence of data from a second respective sequence of memory locations in the memory array; and
directly reading data from the memory array during a random read memory access thereto to read out data stored in one memory location of the first respective sequence of memory locations without copying it to main memory.
23. The method of claim 22 , wherein
the first sequence of data is a first data block and the block write access writes the first data block into the first respective sequence of memory locations in the memory array;
the second sequence of data is a second data block and the block read access reads out the second data block from the second respective sequence of memory locations in the memory array; and
the data stored in the one memory location is a data byte and the random read memory access reads the data byte out from the one memory location of the first respective sequence of memory locations in the memory array.
24. The method of claim 22 , wherein
the controller includes a read/write block access controller and a random read memory controller,
the read/write block access controller to control the block write access and the block read access to the memory array, and
the random read memory controller to control the memory read access into the memory array.
25. The method of claim 22 , further comprising:
in response to the random read memory access, selectively forming a unidirectional data path from the memory array to a bus; and
in response to the block write access and the block read access, selectively forming a bi-directional data path between the memory array and the bus.