IP Library Granted Patent US 11,893,243
Granted Patent B2
US 11,893,243 · App. 17/495,015 · Granted Feb 6, 2024

Storage system and method for program reordering to mitigate program disturbs

Inventors: Daniel J. Linnen (Naperville, IL); Prakash Subedi (San Jose, CA); Khanfer A. Kukkady (San Jose, CA); Mark Murin (Kfar Saba, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0619G06F3/0604G06F3/0655G06F3/0679G06F12/0246
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Quick Facts
Patent No.
US 11,893,243
App. No.
17/495,015
Granted
Feb 6, 2024
Kind
B2
Abstract

A storage system has a memory that is organized in wordlines. Each wordline has a number of strings. A controller in the storage system changes, in each of the wordlines, which of the strings is a last string programmed. Doing so can unmask a program disturb error when triple-level cells in the memory are used as pseudo-multi-level cells. By unmasking the program disturb error, the controller can detect and correct the error.

Claims (37)

1. A storage system comprising:

a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer and wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments; and

a controller configured to:

for each of a plurality of program cycles, change, in each of the plurality of wordlines and with respect to a prior wordline, which of the plurality of programming segments is a last programming segment programmed;

after the plurality of program cycles, observe a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;

based on the observed pattern, select the certain programming segment to be the last programming segment programmed;

detect a number of program disturb errors in the memory; and

correct the program disturb errors using the error correction operation.

2. The storage system of claim 1 , wherein the memory comprises triple-level cells.

3. The storage system of claim 1 , wherein the memory comprises quad-level cells.

4. The storage system of claim 1 , wherein the controller is further configured to change, in each of the plurality of wordlines, a programming order of at least one other one of the plurality of programming segments.

5. The storage system of claim 4 , wherein the controller is further configured to change, in each of the plurality of wordlines, a programming order of all of the plurality of programming segments.

6. The storage system of claim 1 , wherein the controller is further configured to program a first programming segment in each of the plurality of wordlines first.

7. The storage system of claim 1 , wherein the memory further comprises a plurality of memory dies, and wherein the controller is further configured to change a programming order of at least one of the plurality of programming segments across memory dies.

8. The storage system of claim 1 , wherein the memory further comprises a block of memory cells, and wherein the controller is further configured to change a programming order of at least one of the plurality of programming segments across program-erase cycles of the block.

9. The storage system of claim 1 , wherein the memory further comprises a plurality of blocks of memory cells, and wherein the controller is further configured to randomize a starting programming segment to be programmed in each of the plurality of blocks.

10. The storage system of claim 1 , wherein the controller is further configured to randomize a starting programming segment to be programmed in each of the plurality of wordlines.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a storage system comprising a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer, wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments, and wherein the memory comprises a plurality of memory dies organized in a stripe, a method comprising:

changing, in each memory die in the stripe, which of the plurality of programming segments is a last programming segment programmed;

observing a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;

based on the observed pattern, selecting the certain programming segment to be the last programming segment programmed;

detecting a number of program disturb errors in the memory; and

correcting the program disturb errors using the error correction operation.

13. The method of claim 12 , further comprising:

determining whether data was programmed successfully into a current programming segment.

14. The method of claim 13 , further comprising:

in response to determining that the data was not programmed successfully, generating an error report.

15. The method of claim 13 , further comprising:

in response to determining that the data was programmed successfully, determining whether there are any more programming segments available to be programed.

16. A storage system comprising:

a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer and wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments;

means for, for each of a plurality of program cycles, changing, in each of the plurality of wordlines and with respect to a prior wordline, which of the plurality of programming segments is a last programming segment programmed;

means for, after the plurality of program cycles, observing a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;

means for, based on the observed pattern, selecting the certain programming segment to be the last programming segment programmed;

means for detecting a number of program disturb errors in the memory; and

means for correcting the program disturb errors using the error correction operation.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 058426 FRAME 0815 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0679 →
SECURITY INTEREST Recorded Dec 9, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 058426/0815 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2021
From: LINNEN, DANIEL J.; SUBEDI, PRAKASH; KUKKADY, KHANFER A.; MURIN, MARK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 057714/0475 →