Host memory buffer (HMB) random cache access
Aspects of a storage device are provided that allow a controller to leverage cache to minimize occurrence of HMB address overlaps between different HMB requests. The storage device may include a cache and a controller coupled to the cache. The controller may store in the cache, in response to a HMB read request, first data from a HMB at a first HMB address. The controller may also store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address. The controller may refrain from processing subsequent HMB requests in response to an overlap of the first HMB address with an address range including the second HMB address, and the controller may resume processing the subsequent HMB requests after the first data is stored. As a result, turnaround time delays for HMB requests may be reduced and performance may be improved.
1. A storage device, comprising:
a cache, and
a controller coupled to the cache, wherein the controller is configured to:
store in the cache, in response to a host memory buffer (HMB) read request, first data from a HMB at a first HMB address;
store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address; and
refrain from processing subsequent HMB write requests in response to an overlap of the first HMB address with an address range including the second HMB address.
2. The storage device of claim 1 , wherein the controller is further configured to determine that the first data is not previously stored in the cache and that the second data is not previously stored in the cache, and to store the first data in the cache and to store the second data in the cache in response to the determination.
3. The storage device of claim 1 , wherein the cache includes a first cache line address and a second cache line address, and the controller is further configured to store the first data at the first cache line address and to store the second data at the second cache line address.
4. The storage device of claim 1 , wherein the controller is further configured to free a least recently used (LRU) cache line address, and the second data is stored at the LRU cache line address.
5. The storage device of claim 1 , wherein the HMB read request is in response to a first command and the HMB write request is in response to a second command.
6. The storage device of claim 1 , further comprising:
a first buffer and a second buffer, wherein the first buffer is associated with the HMB read request and the second buffer is associated with the HMB write request.
7. The storage device of claim 6 , wherein the controller is further configured to determine whether the first buffer is free, to store the first data in the cache in response to the determination that the first buffer is free, to determine whether the second buffer is free, and to store the second data in the cache in response to the determination that the second buffer is free.
8. The storage device of claim 6 , wherein the cache includes a first cache line address and a second cache line address, the controller is further configured to store a first pointer to the first cache line address in the first buffer, and to store a second pointer to the second cache line address in the second buffer.
9. The storage device of claim 6 , wherein the cache includes a cache line address, the controller is further configured to determine that the first data and the second data are stored at the cache line address, and the controller is further configured to store a pointer to the cache line address in the first buffer and the second buffer.
10. The storage device of claim 1 , wherein the controller is further configured to determine that the first data is to be stored in the cache in response to the HMB read request, to store the first HMB address in a list prior to the store of the first data in response to the determination, and to remove the first HMB address from the list after the store of the first data.
11. The storage device of claim 10 , wherein the controller is further configured to determine that the second data is to be stored in the cache in response to the HMB write request, to determine from the list that the first HMB address overlaps with the address range including the second HMB address, and to refrain from processing subsequent HMB requests in response to the determinations.
12. The storage device of claim 11 , wherein the controller is further configured to resume processing the subsequent HMB requests after the first data is stored in the cache and the first HMB address is removed from the list.
13. A storage device, comprising:
a cache including a first cache line address and a second cache line address, and
a controller coupled to the cache, wherein the controller is configured to:
store at the first cache line address, in response to a host memory buffer (HMB) read request, first data from a HMB at a first HMB address;
store at the second cache line address, in response to an HMB write request, second data from the HMB at a second HMB address; and
write data to the second HMB address in response to the first HMB address not overlapping with an address range including the second HMB address.
14. The storage device of claim 13 , wherein the controller is further configured to execute a first command based on the first data after the first data is stored at the first cache line address, and to execute a second command based on the second data after the second data is stored at the second cache line address.
15. The storage device of claim 14 , further comprising:
a first buffer and a second buffer, wherein the first buffer is associated with the HMB read request and the second buffer is associated with the HMB write request; and
wherein the controller is further configured to store a first pointer to the first cache line address in the first buffer, and to store a second pointer to the second cache line address in the second buffer; and
wherein the controller is further configured to free the first buffer after executing the first command and to free the second buffer after executing the second command.
16. The storage device of claim 13 , wherein the controller is further configured to determine that the first data is to be stored at the first cache line address in response to the HMB read request, and to store the first HMB address in a list prior to the store of the first data in response to the determination.
17. The storage device of claim 16 , wherein the controller is further configured to remove the first HMB address from the list after the store of the first data.
18. The storage device of claim 16 , wherein the controller is further configured to determine that the second data is to be stored at the second cache line address in response to the HMB write request, to determine from the list that the first HMB address does not overlap with the address range including the second HMB address, and to write the data to the second HMB address in response to the determinations.
19. A storage device, comprising:
a cache including a first cache line address and a second cache line address, and
a controller coupled to the cache, wherein the controller is configured to:
store at the first cache line address, in response to a host memory buffer (HMB) read request, first data from a HMB at a first HMB address;
store at the second cache line address, in response to an HMB write request, second data from the HMB at a second HMB address;
refrain from processing subsequent HMB requests before the first data is stored in response to an overlap of the first HMB address with an address range including the second HMB address; and
resume processing the subsequent HMB requests after the first data is stored.
20. The storage device of claim 19 , further comprising:
a first buffer and a second buffer, wherein the controller is further configured to store a first pointer to the first cache line address in the first buffer, and to store a second pointer to the second cache line address in the second buffer.