IP Library Granted Patent US 11,941,270
Granted Patent B2
US 11,941,270 · App. 17/713,126 · Granted Mar 26, 2024

Data storage device with die-based enhanced thermal management

Inventor: Niles Yang (Mountain View, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0634G06F3/0604G06F3/0653G06F3/0679
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,941,270
App. No.
17/713,126
Granted
Mar 26, 2024
Kind
B2
Abstract

A data storage device includes a non-volatile memory device having a number of memory dies. The data storage device further includes a controller. The controller is configured to poll each of the memory dies at a first predetermined rate for a thermal status bit and determine whether the thermal status bit of at least one memory die of the number of memory dies is an active thermal status bit activated. The controller is further configured to reduce the operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit.

Claims (45)

1. A data storage device, comprising:

a non-volatile memory device including a plurality of memory dies, wherein each of the plurality of memory dies include;

a controller configured to:

poll each of the plurality of memory dies at a first predetermined rate for a thermal status bit;

determine whether the thermal status bit of at least one memory die of the plurality of memory dies is an active thermal status bit;

reduce an operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit;

poll the at least one memory die at a second predetermined rate; and

determine whether the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit.

2. The data storage device of claim 1 , wherein the controller is further configured to:

increase the operating performance of the at least one memory die to a normal operating performance in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit.

3. The data storage device of claim 2 , wherein the controller is further configured to:

maintain polling the one or more memory dies adjacent to the at least one memory die at the second predetermined rate in response to determining the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit.

4. The data storage device of claim 2 , wherein the second predetermined rate is a faster rate than the first predetermined rate.

5. The data storage device of claim 1 , wherein reducing the operating performance of the at least one memory die includes reducing an interface speed of the at least one memory die.

6. The data storage device of claim 5 , wherein reducing the interface speed is a reduction of 50%.

7. The data storage device of claim 1 , wherein the plurality of memory dies are configured to activate the thermal status bit in response to a temperature sensor within the plurality of memory dies determining that a sensed temperature exceeds a predetermined threshold.

8. The data storage device of claim 7 , wherein the predetermined threshold is 80° C.

9. A method performed by a data storage device having a controller coupled to a non-volatile memory device, the method comprising:

polling a plurality of memory dies of the non-volatile memory device for a thermal status bit at a first predetermined rate;

determining whether the thermal status bit of at least one memory die of the plurality of memory dies is an active thermal status bit;

reducing an operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit;

polling the at least one memory die at a second predetermined rate; and

determining whether the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit.

10. The method of claim 9 , further comprising:

increase the operating performance of the at least one memory die to a normal operating performance in response to determining that operating performance of the at least one memory die to a normal operating performance in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit.

11. The method of claim 10 , further comprising maintaining polling one or more memory dies adjacent to the at least one memory die at the second predetermined rate in response to determining the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit.

12. The method of claim 10 , wherein the second predetermined rate is a faster rate than the first predetermined rate.

13. The method of claim 9 , wherein reducing the operating performance of the at least one memory die includes reducing an interface speed of the at least one memory die.

14. The method of claim 13 , wherein reducing the interface speed is a reduction of 50%.

15. The method of claim 9 , wherein the plurality of memory dies each include a temperature sensor configured to activate the thermal status bit in response to a temperature monitored by the temperature sensor exceeding a predetermined threshold.

16. The method of claim 15 , wherein the predetermined threshold is 80° C.

17. A data storage device, comprising:

a non-volatile memory device including a plurality of memory dies, wherein each of the plurality of memory dies include a temperature sensor configured to monitor a temperature; and

a controller configured to:

poll each of the plurality of memory dies at a first predetermined rate for a thermal status bit;

determine whether the thermal status bit of at least one memory die of the plurality of memory dies is an active thermal status bit;

reduce an operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit;

poll the at least one memory die at a second predetermined rate in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit;

determine whether the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit; and

increase the operating performance of the at least one memory die to a normal operating performance in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is not the active thermal status bit.

18. The data storage device of claim 17 , wherein the second predetermined rate is a faster rate than the first predetermined rate.

19. The data storage device of claim 17 , wherein reducing the operating performance of the at least one memory die includes reducing an interface speed of the at least one memory die.

20. The data storage device of claim 17 , wherein the controller is further configured to:

record thermal data for the at least one memory die; and

output the recorded thermal data to an external device.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2022
From: YANG, NILES
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059495/0192 →
Continuity (1)
Related Publication 20230315314A1 · Oct 5, 2023