IP Library Granted Patent US 11,468,955
Granted Patent B2
US 11,468,955 · App. 17/179,107 · Granted Oct 11, 2022

Power shaping and peak power reduction by data transfer throttling

Inventor: Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G11C16/30G06F1/28G06F1/3275G06F1/3278G06F13/16G11C5/14Y02D10/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,468,955
App. No.
17/179,107
Granted
Oct 11, 2022
Kind
B2
Abstract

An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.

Claims (60)

1. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

comparing the bandwidth to a threshold bandwidth;

sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth; and

waiting a predetermined time for sending the information from the host to the connected device responsive to the comparing the bandwidth to the threshold bandwidth indicating that the bandwidth would exceed the threshold bandwidth such that the bandwidth used during the sending of the information does not exceed the threshold bandwidth.

2. The method according to claim 1 , wherein the monitoring of the bandwidth is performed only when a direct memory access request is pending.

3. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

comparing the bandwidth to a threshold bandwidth;

sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth; and

determining if a direct memory access request is pending prior to monitoring the bandwidth from the connected device to the host.

4. The method according to claim 3 , wherein determining if the direct memory access request is pending prior to monitoring the bandwidth from the connected device to the host is performed when a reset has not occurred.

5. The method according to claim 3 , further comprising:

prior to sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth, reducing an available bandwidth from an internal counter.

6. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

comparing the bandwidth to a threshold bandwidth;

sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth; and

determining if a reset condition is present in the host prior to monitoring the bandwidth from the connected device to the host.

7. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

comparing the bandwidth to a threshold bandwidth; and

sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth, wherein:

the comparing the bandwidth to the threshold bandwidth comprises determining whether reading activity in a memory arrangement is below the threshold bandwidth; and

the sending information from the host to the connected device comprises:

performing writing activities at the memory arrangement responsive to the reading activity being below the threshold bandwidth; and

delaying writing activities to be performed at the memory arrangement responsive to the threshold bandwidth being exceeded such that writing activities are performed responsive to the threshold bandwidth not being exceeded.

8. The method according to claim 7 , wherein an amount of time for the delaying writing activities is based upon an amount of time the reading activity is above the threshold bandwidth.

9. The method according to claim 7 , further comprising:

performing the delayed writing activities responsive to the reading activity being below the threshold bandwidth.

10. The method according to claim 7 , wherein the memory arrangement comprises a NAND flash memory arrangement.

11. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

comparing the bandwidth to a threshold bandwidth; and

sending information from the host to the connected device responsive to the bandwidth not exceeding the threshold bandwidth, wherein:

monitoring the bandwidth comprises:

receiving data from the host at the connected device; and

interacting with at least a memory array of the connected device;

checking the bandwidth comprises:

measuring the threshold bandwidth for a device controller of the connected device; and

passing data through the device controller responsive to the bandwidth of the device controller being one of at and below the threshold bandwidth; and

sending information from the host to the connected device comprises:

incrementing an internal counter for an amount of the bandwidth to be consumed, wherein any consumed bandwidth is decremented by the internal counter responsive to a read/write command being issued.

12. The method of claim 11 , wherein the connected device comprises at least one interface configured to carry transmitted data from the connected device to the host.

13. The method of claim 11 , wherein at least one component in the device controller is configured to convert data from a digital format to an analogue format and assemble data into packets for transmission.

14. The method of claim 13 , wherein the connected device comprises:

a command fetcher connected to the at least one component wherein the command fetcher is configured to accept commands; and

a command executor connected to the command fetcher wherein the command executor is configured to execute commands.

15. The method of claim 14 , wherein the connected device further comprises at least one processor configured to perform calculations for the device controller.

16. The method of claim 11 , wherein the connected device comprises a scheduler configured to schedule activities of the device controller.

17. The method claim 11 , wherein the connected device comprises a direct memory access arrangement configured to access data from a data transfer throttling arrangement.

18. The method of claim 11 , wherein the connected device comprises:

at least one memory array; and

a flash interface module configured to interface with the at least one memory array.

19. A memory device, comprising:

means for monitoring a bandwidth of one of a write operation and a read operation from the memory device to a host;

means for comparing the bandwidth to a threshold bandwidth;

means for sending information from the host to the memory device responsive to the bandwidth not exceeding the threshold bandwidth; and

means for waiting a predetermined time for sending the information from the host to a connected device responsive to the comparing the bandwidth to the threshold bandwidth indicating that the bandwidth would exceed the threshold bandwidth such that the bandwidth used during the sending of the information does not exceed the threshold bandwidth.

20. The method of claim 11 , wherein the device comprises a flash interface module configured to interface with at least one memory array.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2021
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055336/0896 →
Continuity (3)
Division 16452468 · Jun 25, 2019
Division 15838502 · Dec 12, 2017
Related Publication 20210174883A1 · Jun 10, 2021