Power shaping and peak power reduction by data transfer throttling
An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.
1. A device configured to transmit data to and receive data from a host, the device comprising:
at least one memory array; and
a device controller comprising:
a flash interface module configured to interface with the at least one memory array;
a physical layer interface (phy);
a direct memory access (DMA) arrangement; and
a data transfer throttling arrangement coupled to the DMA arrangement and configured to:
measure a bandwidth for the phy; and
pass a DMA request through the phy to the host in response to the bandwidth of the phy being either at or below a threshold
wherein the data transfer throttling arrangement is coupled either:
between the DMA arrangement and the phy; or
within the flash interface module.
2. The device according to claim 1 , wherein the device controller comprises at least one layer configured to:
convert data from a digital format to an analogue format; and
assemble data into packets for transmission.
3. The device according to claim 2 , wherein the device controller further comprises:
a scheduler configured to schedule activities of the device controller.
4. The device according to claim 1 , wherein the device controller further comprises:
at least one processor configured to perform calculations for the device controller.
5. The device according to claim 4 , wherein the device controller further comprises:
a command fetcher configured to accept commands; and
a command executor connected to the command fetcher wherein the command executor is configured to execute commands.
6. The device according to claim 4 , wherein the device further comprises
an error correction arrangement.
7. The device according to claim 1 , wherein the DMA arrangement is configured to access data from the data transfer throttling arrangement.
8. A device configured to transmit data to and receive data from a host, the device comprising:
at least one memory array;
an interface means for interacting with the at least one memory array;
an interface means for interacting with the host;
a direct memory access (DMA) means for handling a DMA request; and
a data transfer throttling means for passing the DMA request through the interface means for interacting with the host responsive to the interface means for interacting with the host being at or below a bandwidth threshold,
wherein the data transfer throttling means is coupled either:
between the DMA means and the interface means for interacting with the host; or
within the interface means for interacting with the at least one memory array.
9. The device of claim 8 , further comprising means to:
convert data from a digital format to an analogue format; and
assemble data into packets for transmission.
10. The device of claim 9 , further comprising means to schedule activities of a device controller.
11. The device of claim 8 , further comprising means to perform calculations.
12. The device of claim 11 , further comprising means to accept commands.
13. The device of claim 8 , further comprising
an error correction arrangement.
14. The device of claim 8 , further comprising means to access data from the data transfer throttling means.
15. A method of operating a data storage device having a direct memory access (DMA) arrangement to store data in one or more memory arrays, the method comprising:
determining that there is a pending DMA request;
measuring a bandwidth for a physical layer interface (phy) with a data transfer throttling arrangement in response to the pending DMA request; and
passing data a DMA request through the phy in response to the bandwidth of the phy being either at or below a threshold, wherein the data transfer throttling arrangement is coupled either:
between a DMA arrangement and the phy; or
within a flash interface module.
16. The method of claim 15 , further comprising:
converting data from a digital format to an analogue format; and
assembling data into packets for transmission.
17. The method of claim 16 , further comprising scheduling commands for the device controller.
18. The device according to claim 1 , wherein the data transfer throttling arrangement is configured to delay the DMA request to the phy in response to the bandwidth of the phy exceeding the threshold.
19. The device according to claim 8 , wherein the data transfer throttling means is configured to delay the DMA request to the interface means for interacting with the host in response to the bandwidth of the interface means for interacting with the host exceeding the threshold.
20. The method according to claim 15 , further comprising delaying the DMA request to the phy in response to the bandwidth of the phy exceeding the threshold.