Dual slc/qlc programming and resource releasing
The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.
1. A data storage device, comprising:
one or more memory devices, the one or more memory devices including SLC memory and MLC memory; and
a controller coupled to the one or more memory devices, the controller configured to perform the following sequentially:
write data to the SLC memory;
foggy write the data to MLC memory, wherein the foggy writing the data to the MLC memory occurs in parallel to the writing data to the SLC memory using the same data buffer;
receive a first release request to release the same data buffer, wherein the first release request indicates that either the writing the data to the SLC memory or the foggy writing the data to the MLC memory has completed;
receive a second release request to release the same data buffer, wherein the second release request indicates that either the writing the data to the SLC memory or the foggy writing the data to the MLC memory has completed;
release the same data buffer once the foggy write to MLC memory has completed and the writing data to the SLC memory has completed, wherein the same data buffer is a single data buffer, wherein the controller is further configured to release the same data buffer upon receiving both the first release request and the second release request; and then
read the data from the SLC memory; and
fine writing the data read from SLC memory to the MLC memory.
2. The data storage device of claim 1 , wherein the data read from the SLC memory passes through a relocation buffer storage device.
3. The data storage device of claim 2 , wherein the data passes through the relocation buffer a single time prior to being written to the MLC memory.
4. The data storage device of claim 1 , wherein the data passes through a relocation buffer after reading the data from SLC memory and prior to fine writing the data to MLC memory.
5. The data storage device of claim 4 , wherein the relocation buffer and the same buffer are distinct.
6. The data storage device of claim 1 , wherein the MLC memory is QLC memory.
7. The data storage device of claim 1 , wherein the data exits the same buffer two times.
8. The data storage device of claim 1 , further comprising a dual releaser coupled to the controller.
9. The data storage device of claim 8 , wherein the dual releaser includes a dual release register, an internal interconnect, a re-release access manipulator, and a dual releaser bitmap register.
10. The data storage device of claim 1 , further comprising a resource server.
11. The data storage device of claim 10 , wherein the resource server includes a resource release register.
12. The data storage device of claim 10 , wherein the resource server is coupled to a dual releaser.
13. The data storage device of claim 12 , wherein the dual releaser is coupled to the controller, the one or more memory devices, and the same buffer.
14. The data storage device of claim 1 , wherein the controller is configured to release the same buffer to an available buffer pool upon determining that two buffer release requests have been received.
15. The data storage device of claim 14 , wherein the controller is further configured to hold data in the same buffer until the same buffer has been released.
16. The data storage device of claim 14 , wherein the two release requests are received independently.
17. The data storage device of claim 1 , wherein the same buffer is SRAM.
18. The data storage device of claim 1 , further comprises an interface for ingress of communications from a host to the data storage device and from the data storage device to the host.
19. The data storage device of claim 1 , further comprises a command processing module configured to implement collision logic while implementing a collision table.
20. The data storage device of claim 19 , wherein the collision table holds logical block addresses (LBA) that are cached.