Optimized SSD for game loading and rendering
Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.
1. A storage device, comprising:
non-volatile memory; and
a controller configured to:
receive from a host a read command indicating a logical address;
read host data associated with a predicted logical address that is subsequent to the logical address from the non-volatile memory in response to the read command;
load the host data in a memory buffer in host volatile memory that is accessible to the host and to the controller, the memory buffer being dedicated for predicted host data; and
subsequently receive from the host a subsequent read command indicating the predicted logical address, the subsequent read command lacking an address of a physical region page (PRP) specified in the read command for data transfer in response to the host data being loaded in the memory buffer.
2. The storage device of claim 1 , wherein the memory buffer dedicated for the predicted host data is a read-look-ahead memory buffer (RMB) that is different than a host memory buffer (HMB).
3. The storage device of claim 1 , wherein the controller is further configured to:
receive a vendor-specific command requesting the controller to allocate the memory buffer in a portion of the host volatile memory, wherein the host data is loaded after the memory buffer is allocated.
4. The storage device of claim 1 , wherein the controller is further configured to:
predict a subsequent logical address to the logical address indicated in the read command, the predicted logical address being the subsequent logical address.
5. The storage device of claim 1 , wherein the read command from the host indicates the predicted logical address.
6. The storage device of claim 1 , wherein the controller is further configured to:
load, in the host volatile memory, a logical-to-physical (L2P) mapping of the predicted logical address to a physical address of the memory buffer.
7. The storage device of claim 1 , wherein the controller is further configured to:
refrain from subsequently reading the host data associated with the predicted logical address from the non-volatile memory in response to reception of the subsequent read command from the host for the host data or in response to a lack of additional subsequent read commands from the host for the host data.
8. The storage device of claim 1 , wherein the controller is further configured to:
update a completion queue with a completion queue element indicating a list of PRPs in the memory buffer in response to the subsequent read command.
9. The storage device of claim 8 , wherein the list of PRPs is indicated in a status field of the completion queue element.
10. The storage device of claim 1 , wherein the controller is further configured to:
receive a release command from the host indicating a release of the memory buffer; and
free the memory buffer in response to the release command, wherein the host data is loaded in the memory buffer after the memory buffer is freed.
11. The storage device of claim 1 , wherein the memory buffer includes a plurality of bitmaps respectively indicating a status of each of a plurality of buffers within the memory buffer.
12. The storage device of claim 11 ,
wherein the bitmaps include a first bitmap and a second bitmap respectively indicating free buffers and occupied buffers of the plurality of buffers, the first bitmap being write accessible to the controller and read accessible to the host, and the second bitmap being write accessible to the host and read accessible to the controller;
wherein the occupied buffers indicated in the first bitmap include predicted host data and the occupied buffers indicated in the second bitmap include processed predicted host data.
13. The storage device of claim 12 , wherein the controller is further configured to:
update the first bitmap in response to a release command from the host indicating a release of one or more of the occupied buffers.
14. A storage device, comprising:
non-volatile memory; and
a controller configured to:
obtain a bitmap indicating a status of a buffer in a memory buffer in host volatile memory, the memory buffer being accessible to a host and to the controller and being dedicated for predicted host data;
predict, in response to a read command from the host indicating a logical address, a subsequent logical address to the logical address;
read host data at the subsequent logical address from the non-volatile memory; and
load the host data in the buffer in the memory buffer in response to the bitmap indicating the buffer is free.
15. The storage device of claim 14 , wherein the bitmap indicates a plurality of free buffers and a plurality of occupied buffers in the memory buffer including the buffer, the bitmap being write accessible to the controller and read accessible to the host.
16. The storage device of claim 14 , wherein the controller is further configured to:
receive a release command from the host indicating a release of the buffer in the memory buffer;
update the bitmap in response to the release command; and
free the buffer in the memory buffer in response to the release, wherein the host data is loaded in the buffer in the memory buffer after the buffer is freed and the bitmap is updated.
17. The storage device of claim 16 , wherein the release command includes a second bitmap indicating a plurality of occupied buffers in the memory buffer including the buffer, the second bitmap being write accessible to the host and read accessible to the controller.
18. A storage device, comprising:
non-volatile memory; and
a controller configured to:
obtain a bitmap indicating a status of a buffer in a memory buffer in host volatile memory that is accessible to a host and to the controller, the memory buffer being dedicated for predicted host data;
receive from the host a vendor-specific read command indicating a logical address;
read host data associated with a predicted logical address that is subsequent to the logical address from the non-volatile memory in response to the vendor-specific read command; and
load the host data in the buffer in the memory buffer in response to the bitmap indicating the buffer is free.
19. The storage device of claim 18 , wherein the controller is further configured to:
receive a vendor-specific release command from the host indicating a release of the buffer in the memory buffer;
update the bitmap in response to the vendor-specific release command; and
free the buffer in the memory buffer in response to the release, wherein the host data is loaded in the buffer in the memory buffer after the buffer is freed and the bitmap is updated.
20. The storage device of claim 18 , wherein the controller is further configured to:
receive from the host a second bitmap, the bitmap and the second bitmap respectively indicating a plurality of free buffers and a plurality of occupied buffers in the memory buffer including the buffer, and
wherein the bitmap is write accessible to the controller and read accessible to the host, and the second bitmap is write accessible to the host and read accessible to the controller.