IP Library Granted Patent US 11,798,918
Granted Patent B2
US 11,798,918 · App. 17/539,062 · Granted Oct 24, 2023

Ball grid array substrate

Inventors: Muhammad Bashir Mansor (Kubang Semang, MY); Chong Un Tan (Seremban, MY); Shivaram Sahadevan (Kulim, MY); Mickaldass Santanasamy (George Town, MY); Muhammad Faizul Mohd Yunus (Simpang Ampat, MY); Chin Koon Tang (Bayan Lepas, MY)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H01L25/0657H01L23/49816H01L23/49833H01L2225/0651H01L2225/06506H01L2225/06562
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Quick Facts
Patent No.
US 11,798,918
App. No.
17/539,062
Granted
Oct 24, 2023
Kind
B2
Abstract

A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.

Claims (42)

1. An apparatus, comprising:

an integrated circuit die (ICD) substrate having a top surface and a bottom surface, the top surface including a plurality of die contact pads;

a plurality of solder balls at least partially embedded in the bottom surface of the ICD substrate, wherein one or more of the solder balls is in electrical communication with one or more of the die contact pads;

one or more integrated circuit dies attached to the top surface of the ICD substrate and in electrical communication with the die contact pads of the ICD substrate, the one or more integrated circuit dies comprises a plurality of dies that are stacked and laterally offset relative to an adjacent one of the plurality of dies such that a plurality of electrical contacts along edges of the plurality of dies are exposed;

a plurality of bond wires extending between the die electrical contacts and the ICD substrate die contact pads; and

a printed circuit board (PCB) substrate comprising:

a top surface and a bottom surface;

a plurality of cavities formed in the top surface that each correspond to and align with one of the plurality of solder balls; and

a die attach film (DAF) disposed on the top surface of the PCB substrate, wherein the DAF includes an opening for each cavity of the plurality of cavities.

2. The apparatus of claim 1 , wherein the plurality of solder balls forms a ball grid array of solder balls and the plurality of cavities receive flux.

3. The apparatus of claim 2 , wherein the flux is disposed in each of the plurality of cavities and forms an exposed flux surface that is substantially parallel planar to the top surface of the PCB substrate.

4. The apparatus of claim 3 , wherein each opening of the DAF exposes the exposed flux surface.

5. The apparatus of claim 1 , wherein the PCB substrate comprises multiple layers electrically connecting the one or more integrated circuit dies through the plurality of die contact pads and the plurality of solder balls to a plurality of additional integrated circuit dies electrically coupled to the PCB substrate.

6. The apparatus of claim 1 , wherein a first portion of the plurality of dies are laterally offset in a first direction to expose a first edge of each of the plurality of dies, and a second portion of the plurality of dies are laterally offset in a second direction to expose a second edge of each of the plurality of dies.

7. The apparatus of claim 1 , wherein the bond wires electrically couple each of the plurality of dies with the ICD substrate to enable electrical communication between each of the plurality of dies and the ICD substrate.

8. The apparatus of claim 1 , further comprising an encapsulation material formed around the plurality of dies.

9. The apparatus of claim 1 , wherein each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface of the ICD substrate.

10. A system, comprising:

an integrated circuit die (ICD) substrate having a top surface and a bottom surface;

one or more integrated circuit dies attached to the top surface of the ICD substrate, the one or more integrated circuit dies comprises a plurality of dies that are stacked and laterally offset relative to an adjacent one of the plurality of dies such that a plurality of electrical contacts along edges of the plurality of dies are exposed;

a plurality of bond wires extending between the die electrical contacts and die contact pads on the top surface of the ICD substrate;

a plurality of solder balls at least partially embedded in the bottom surface of the ICD substrate wherein the one or more dies are in electrical communication with the plurality of solder balls by way of the ICD substrate;

a printed circuit board (PCB) substrate having a top surface including a plurality of cavities configured to store flux and to receive exposed surfaces of the plurality of solder balls; and

a die attach film (DAF) disposed between and securing the ICD substrate and the PCB substrate, wherein the DAF comprises a plurality of openings that each correspond with one of the plurality of cavities.

11. The system of claim 10 , wherein the plurality of solder balls forms a grid array of solder balls and the flux is disposed in each of the plurality of cavities and forms an exposed flux surface that is substantially parallel planar to the top surface of the PCB substrate.

12. The system of claim 11 , wherein the plurality of openings expose the exposed flux surface.

13. The system of claim 10 , further comprising:

a plurality of additional integrated circuit dies electrically coupled to the PCB substrate; and

a plurality of electrical interconnects disposed in the PCB substrate between the one or more integrated circuit dies and the plurality of additional integrated circuit dies.

14. The system of claim 11 , wherein a first portion of the plurality of dies are laterally offset in a first direction to expose a first edge of each of the plurality of dies, and a second portion of the plurality of dies are laterally offset in a second direction to expose a second edge of each of the plurality of dies.

15. The system of claim 10 , further comprising an encapsulation material formed around the plurality of dies.

16. The system of claim 10 , wherein the bonding wire electrically couples each of the plurality of dies with the ICD substrate to enable electrical communication between each of the plurality of dies and the ICD substrate.

17. An apparatus comprising:

first substrate means having a top surface and a bottom surface;

one or more integrated circuit dies attached to the top surface of the first substrate means, the one or more integrated circuit dies comprises a plurality of dies that are stacked and laterally offset relative to an adjacent one of the plurality of dies such that a plurality of electrical contacts along edges of the plurality of dies are exposed;

means for electrically connecting the plurality of die electrical contacts with respective die contact pads on a top surface of the first substrate means;

a plurality of solder balls embedded in a bottom surface of the first substrate means, wherein the one or more integrated circuit dies are in electrical communication with the plurality of solder balls by way of the first substrate means;

second substrate means having a plurality of cavities in a top surface thereof, and

means for adhering the bottom surface of the first substrate means with the top surface of the second substrate means.

18. The apparatus of claim 17 , further comprising means for encapsulating the one or more integrated circuit dies.

19. The apparatus of claim 17 , wherein the means for adhering includes an opening for each of the cavities.

20. The apparatus of claim 17 , wherein a first portion of the plurality of dies are laterally offset in a first direction to expose a first edge of each of the plurality of dies, and a second portion of the plurality of dies are laterally offset in a second direction to expose a second edge of each of the plurality of dies.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2023
From: MANSOR, MUHAMMAD BASHIR; TAN, CHONG UN; SAHADEVAN, SHIVARAM; SANTANASAMY, MICKALDASS; YUNUS, MUHAMMAD FAIZUL MOHD; TANG, CHIN KOON
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 062374/0138 →