IP Library Granted Patent US 8,135,903
Granted Patent B1
US 8,135,903 · App. 12/610,129 · Granted Mar 13, 2012

Non-volatile semiconductor memory compressing data to improve performance

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Quick Facts
Patent No.
US 8,135,903
App. No.
12/610,129
Granted
Mar 13, 2012
Kind
B1
Abstract

A non-volatile semiconductor memory is disclosed comprising a plurality of paired pages, wherein each pair comprises a first page and a second page. A write command is received from a host comprising write data and a write address. The write address is mapped to a physical address of a selected one of the paired memory pages. The write data is compressed to generate compressed data, and when the compressed data fits in one of the pages of the selected pair, the compressed data is stored in the first page and in the second page of the selected pair in an S-mode.

Claims (40)

1. A non-volatile semiconductor memory comprising:

a plurality of paired pages, wherein each pair comprises a first page and a second page; and

control circuitry operable to:

receive a write command from a host comprising write data and a write address;

map the write address to a physical address of a selected one of the paired memory pages;

compress the write data to generate compressed data; and

when the compressed data fits in one of the pages of the selected pair, store the compressed data in the first page and in the second page of the selected pair in an S-mode.

2. The non-volatile semiconductor memory as recited in claim 1 , wherein when the compressed data does not fit in one of the pages of the selected pair, the control circuitry is further operable to store the compressed data in the first page and in the second page of the selected pair in an M-mode.

3. The non-volatile semiconductor memory as recited in claim 1 , wherein:

the first and second page of the selected pair comprises a plurality of cells; and

each cell stores a single bit in the S-mode.

4. The non-volatile semiconductor memory as recited in claim 2 , wherein:

the first and second page of the selected pair comprises a plurality of cells; and

each cell stores multiple bits in the M-mode.

5. The non-volatile semiconductor memory as recited in claim 1 , wherein the compressed data further comprises a size parameter of the compressed data.

6. The non-volatile semiconductor memory as recited in claim 5 , wherein the control circuitry is further operable to:

receive a read command from the host comprising a read address;

map the read address to one of the paired pages;

read the size parameter from the paired pages; and

when the size parameter indicates the compressed data did not fit into one of the paired pages, read the compressed data from the first and second pages.

7. The non-volatile semiconductor memory as recited in claim 1 , wherein when the compressed data does not fit in one of the pages of the selected pair, the control circuitry is further operable to store the write data in the first page and in the second page of the selected pair in an M-mode.

8. A method of operating a non-volatile semiconductor memory comprising a plurality of paired pages, wherein each pair comprises a first page and a second page, the method comprising:

receiving a write command from a host comprising write data and a write address;

mapping the write address to a physical address of a selected one of the paired memory pages;

compressing the write data to generate compressed data; and

when the compressed data fits in one of the pages of the selected pair, storing the compressed data in the first page and in the second page of the selected pair in an S-mode.

9. The method as recited in claim 8 , wherein when the compressed data does not fit in one of the pages of the selected pair, further comprising storing the compressed data in the first page and in the second page of the selected pair in an M-mode.

10. The method as recited in claim 8 , wherein:

the first and second page of the selected pair comprises a plurality of cells; and

each cell stores a single bit in the S-mode.

11. The method as recited in claim 9 , wherein:

the first and second page of the selected pair comprises a plurality of cells; and

each cell stores multiple bits in the M-mode.

12. The method as recited in claim 8 , wherein the compressed data further comprises a size parameter of the compressed data.

13. The method as recited in claim 12 , further comprising:

receiving a read command from the host comprising a read address;

mapping the read address to one of the paired pages;

reading the size parameter from the paired pages; and

when the size parameter indicates the compressed data did not fit into one of the paired pages, reading the compressed data from the first and second pages.

14. The method as recited in claim 8 , wherein when the compressed data does not fit in one of the pages of the selected pair, further comprising storing the write data in the first page and in the second page of the selected pair in an M-mode.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2010
From: KAN, ALAN CHINGTAO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 023801/0991 →