IP Library Granted Patent US 10,732,838
Granted Patent B2
US 10,732,838 · App. 15/885,767 · Granted Aug 4, 2020

Logical grouping for hybrid dual write

Inventors: Noor Mohamed (Thanjavur, IN); Athira Kanchiyil (Bangalore, IN); Sharad Gupta (Bangalore, IN); Arunkumar Mani (Thirunelveli, IN); Silky Mohanty (Bhubaneswar, IN); Arun Kumar Shukla (Bangalore, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0604G06F3/065G06F3/0631G06F3/0644G06F3/0659G06F3/0679G11C5/148G11C7/1015G11C11/56G11C11/5628G11C16/10G06F12/0223G06F2212/205G11C29/04G11C29/52G11C2211/5641
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Quick Facts
Patent No.
US 10,732,838
App. No.
15/885,767
Granted
Aug 4, 2020
Kind
B2
Abstract

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks. In response to a multi level writing circuit copying data from a set of single level cell blocks to a plurality of multi level cell blocks, a first portion of data from the set of single level cell blocks remains uncopied because the first portion of data is insufficient to fill an entire multi level cell block.

Claims (37)

1. An apparatus comprising:

a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks; and

a hybrid writing component comprising:

a single level writing circuit configured to write data to the plurality of single level cell blocks;

a multi level writing circuit configured to copy the data from the plurality of single level cell blocks to the plurality of multi level cell blocks, wherein the plurality of multi level cell blocks are flash memory cell blocks; and

a grouping circuit configured to:

direct the single level writing circuit to write data corresponding to a first logical group of data to a first set of single level cell blocks of the plurality of single level cell blocks and to write data corresponding to a second logical group of data to a second set of single level cell blocks of the plurality of single level cell blocks, wherein, in response to the multi level writing circuit copying data from the first set of single level cell blocks to the plurality of multi level cell blocks and from the second set of single level cell blocks to the plurality of multi level cell blocks, a first portion of data from the first set of single level cell blocks remains uncopied because the first portion of data is insufficient to fill an entire multi level cell block and a second portion of data from the second set of single level cell blocks remains uncopied because the second portion of data is insufficient to fill an entire multi level cell block; and

in response to the first portion of data and the second portion of data being sufficient to fill an entire multi level cell block, copy the first portion of data and the second portion of data to a corresponding multi level cell block of the plurality of multi level cell blocks.

2. The apparatus of claim 1 , wherein the hybrid writing component further comprises a delay circuit configured to wait a predetermined period of time for additional data to combine with the first portion of data.

3. The apparatus of claim 2 , wherein the additional data is part of the first logical group of data.

4. The apparatus of claim 2 , wherein the additional data is part of the second logical group of data.

5. The apparatus of claim 2 , wherein the first portion of data and the additional data are part of a same update group of data.

6. The apparatus of claim 2 , wherein the first portion of data and the additional data are part of different update groups of data.

7. The apparatus of claim 1 , wherein a portion of each single level cell block of the plurality of single level cell blocks is unavailable for storing data.

8. The apparatus of claim 7 , wherein the portion comprises 16 pages.

9. The apparatus of claim 1 , further comprising a verification circuit configured to verify the data stored on the plurality of multi level cell blocks.

10. The apparatus of claim 9 , further comprising a recycling circuit configured to reuse single level cell blocks of the plurality of single level cell blocks corresponding to verified multi level cell blocks of the plurality of multi level cell blocks.

11. A method comprising:

writing data corresponding to a first set of single level cell blocks and a second set of single level cell blocks;

copying a first portion of the data from the first set of single level cell blocks to one or more multi level cell blocks, wherein the one or more multi level cell blocks are flash memory cell blocks;

copying a second portion of additional data from the second set of single level cell blocks to the one or more multi level cell blocks;

determining that a third portion of the data from the first set of single level cell blocks remains uncopied to the one or more multi level cell blocks because the third portion of the data is insufficient to fill an entire multi level cell block;

determining that a fourth portion of the additional data from the second set of single level cell blocks remains uncopied to the one or more multi level cell blocks because the fourth portion of the additional data is insufficient to fill an entire multi level cell block; and

in response to determining that the third portion of the data and the fourth portion of the additional data are sufficient to fill an entire multi level cell block, copying the third portion of the data and the fourth portion of the additional data to a corresponding multi level cell block of the one or more multi level cell blocks.

12. The method of claim 11 , further comprising pausing for a period of time to determine whether the additional data is available to combine with the third portion of data.

13. The method of claim 12 , wherein the data is part of a first logical group of data and the additional data is part of the first logical group of data.

14. The method of claim 12 , wherein the data is part of a first logical group of data and the additional data is part of a second logical group of data.

15. The method of claim 12 , wherein the second portion of data and the additional data are part of a same update group of data.

16. The method of claim 12 , wherein the second portion of data and the additional data are part of different update groups of data.

17. An apparatus comprising:

means for writing data corresponding to a first set of single level cell blocks and a second set of single level cell blocks;

means for copying a first portion of the data from the first set of single level cell blocks to one or more multi level cell blocks, wherein the one or more multi level cell blocks are flash memory cell blocks;

means for copying a second portion of additional data from the second set of single level cell blocks to the one or more multi level cell blocks;

means for determining that a third portion of the data from the first set of single level cell blocks remains uncopied to the one or more multi level cell blocks because the third portion of the data is insufficient to fill an entire multi level cell block;

means for determining that a fourth portion of the additional data from the second set of single level cell blocks remains uncopied to the one or more multi level cell blocks because the fourth portion of the additional data is insufficient to fill an entire multi level cell block; and

means for, in response to determining that the third portion of the data and the fourth portion of the additional data are sufficient to fill an entire multi level cell block, copying the third portion of the data and the fourth portion of the additional data to a corresponding multi level cell block of the one or more multi level cell blocks.

18. The apparatus of claim 17 , wherein the third portion of the data and the fourth portion of the additional data comprise different logical groups of data.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2018
From: MOHAMED, NOOR; KANCHIYIL, ATHIRA; GUPTA, SHARAD; MANI, ARUNKUMAR; MOHANTY, SILKY; SHUKLA, ARUN KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047643/0354 →
Continuity (1)
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