IP Library Granted Patent US 10,747,454
Granted Patent B1
US 10,747,454 · App. 16/259,828 · Granted Aug 18, 2020

Data storage systems and methods for self adaptive chip-enable setup time

Inventors: Niang-Chu Chen (Irvine, CA); Jun Tao (Ladera Ranch, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0632G06F3/061G06F3/0634G06F3/0659G06F3/0679G06F11/3034G06F2201/88
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Quick Facts
Patent No.
US 10,747,454
App. No.
16/259,828
Granted
Aug 18, 2020
Kind
B1
Abstract

Apparatus, media, methods, and systems for data storage systems and methods for self-adaptive chip-enable setup time. A data storage system may comprise one or more non-volatile memory device and a controller. The controller is configured to determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped. The controller is configured to, when the command to the first non-volatile memory device is determined to be dropped, increase a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device.

Claims (71)

1. A data storage system, comprising:

one or more non-volatile memory devices; and

a controller,

wherein the controller is configured to:

determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped;

when the command to the first non-volatile memory device is determined to be dropped,

update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and

increase, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration; and

when the command to the first non-volatile memory device is determined to be not dropped,

update a second counter value associated with the first non-volatile memory device;

determine whether the second counter value satisfies a threshold value; and

when the second counter value satisfies the threshold value,

decrease the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time duration.

2. The data storage system of claim 1 , wherein the controller is configured to:

when the second counter value satisfies the threshold value,

determine, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time duration.

3. The data storage system of claim 1 , wherein the controller is configured to:

when the second counter value satisfies the threshold value,

determine whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and

when the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter,

decrease the value of the chip-enable setup time parameter by the second time duration.

4. The data storage system of claim 1 , wherein the second counter value indicates a number of consecutive commands to the first non-volatile memory device that are not dropped.

5. The data storage system of claim 1 , wherein the one or more parameter values are based on at least one of manufacturing variance of the first non-volatile memory device and calibration of the first non-volatile memory device.

6. The data storage system of claim 1 , wherein the first time duration is configurable for the first non-volatile memory device, based on at least one of manufacturing variance of the first non-volatile memory device and calibration of the first non-volatile memory device.

7. The data storage system of claim 1 , wherein the controller is configured to:

determine whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and

when the command to the second non-volatile memory device is determined to be dropped,

increase, based on at least one of a third counter value and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time period, wherein the third time period is different from the first time duration and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.

8. A computer-implemented method for a data storage system, comprising:

determining whether a command to a first non-volatile memory device of one or more non-volatile memory devices is dropped;

in response to determining that the command to the first non-volatile memory device is dropped:

updating a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and

increasing, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, wherein the first time duration is configurable for the first non-volatile memory device; and

in response to determining that the command to the first non-volatile memory device is not dropped:

updating a second counter value associated with the first non-volatile memory device;

determining whether the second counter value satisfies a threshold value; and

in response to determining that the second counter value satisfies the threshold value:

decreasing the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time duration.

9. The computer-implemented method of claim 8 , further comprising:

determining, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time duration.

10. The computer-implemented method of claim 8 , further comprising:

determining whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and

in response to determining that the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter:

decreasing the value of the chip-enable setup time parameter by the second time duration.

11. The computer-implemented method of claim 8 , wherein the second counter value indicates a consecutive number of commands to the first non-volatile memory device that are not dropped.

12. The computer-implemented method of claim 8 , wherein the threshold value is a timer value, and the first counter value is associated with the first non-volatile memory device.

13. The computer-implemented method of claim 8 , further comprising:

determining whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and

in response to determining that the command to the second non-volatile memory device is determined to be dropped:

increasing, based on at least one of a third counter value, and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time duration, wherein the third time duration is different from the first time duration and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.

14. A data storage system, comprising:

one or more non-volatile memory devices;

means for determining whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped;

in response to determining that the command to the first non-volatile memory device is dropped:

means for updating a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and

means for increasing, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time period; and

in response to determining that the command to the first non-volatile memory device is not dropped:

means for updating a second counter value associated with the first non-volatile memory device;

means for determining whether the second counter value satisfies a threshold value; and

in response to determining that the second counter value satisfies the threshold value:

means for decreasing the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time period.

15. The data storage system of claim 14 , comprising:

means for determining, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time period.

16. The data storage system of claim 14 , comprising:

means for determining whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and

in response to determining that the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter:

means for decreasing the value of the chip-enable setup time parameter by the second time period.

17. The data storage system of claim 14 , comprising:

means for determining whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and

in response to determining that the command to the second non-volatile memory device is determined to be dropped:

means for increasing, based on at least one of a third counter value and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time period, wherein the third time period is different from the first time period and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: CHEN, NIANG-CHU; TAO, JUN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048196/0303 →