Granted Patent B2

US 10,558,522 · App. 15/789,890 · Granted Feb 11, 2020

Inventors: Jun Tao (Ladera Ranch, CA); Niang-Chu Chen (Irvine, CA); Mark Joseph Dancho (Chandler, AZ); Xiaoheng Chen (Dublin, CA)

Assignee: Western Digital Technologies, Inc.

G06F11/1068G11C29/021G11C29/028G11C29/52H03M13/1108H03M13/1111H03M13/3715H03M13/6325

Abstract

Claims (104)

1. A machine-implemented method, comprising:

selecting a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator;

executing a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage;

returning decoded data from the preliminary hard decoding operation when the preliminary hard decoding operation is successful;

when the preliminary hard decoding operation is unsuccessful:

executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the sequence of read-level voltages; and

returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and

maintaining the decoding success indicator based on results of the preliminary hard decoding operation or the multi-stage decoding operation,

wherein when a first hard decoding operation using a first read-level voltage of the sequence of read-level voltages is unsuccessful, a next decoding operation that follows the first hard decoding operation is a first soft decoding operation regardless of whether a second hard decoding operation is available,

wherein the first soft decoding operation is associated with the first read-level voltage,

wherein when the first soft decoding operation is performed, the first soft decoding operation is performed without re-reading the plurality of memory cells,

wherein when the first soft decoding operation is unsuccessful, the first soft decoding operation is followed by a second soft decoding operation associated with the first read-level voltage,

wherein when the second soft decoding operation is performed, the second soft decoding operation is performed without re-reading the plurality of memory cells,

wherein the first hard decoding operation is (a) the preliminary hard decoding operation or (b) a hard decoding operation of the multi-stage decoding operation, and

wherein the first read-level voltage is (x) the preliminary read-level voltage or (y) a respective read-level voltage, from the sequence of read-level voltages, corresponding to a stage of the multi-stage decoding operation.

2. The machine-implemented method of claim 1 , wherein each stage of the multi-stage decoding operation comprises executing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read-level voltage from the sequence of read-level voltages corresponding to the stage, and

wherein the stages of the multi-stage decoding operation are executed sequentially until one of the one or more decoding operations in one of the stages successfully decodes the raw data read from the plurality of memory cells.

3. The machine-implemented method of claim 2 , wherein the one or more decoding operations of each stage of the multi-stage decoding operation comprises a hard decoding operation and up to a plurality of soft decoding operations.

4. The machine-implemented method of claim 2 , wherein the decoding success indicator indicates one read-level voltage of the sequence of read-level voltages, and

wherein maintaining the decoding success indicator comprises setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data.

5. The machine-implemented method of claim 2 , further comprising incrementing a counter value corresponding to the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data,

wherein maintaining the decoding success indicator comprises setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages with the highest corresponding counter value.

6. The machine-implemented method of claim 5 , wherein the decoding success indicator is maintained following completion of a number of read requests greater than one since the decoding success indicator was last maintained.

7. The machine-implemented method of claim 2 , further comprising:

buffering the raw data read from the plurality of memory cells using the preliminary read-level voltage,

wherein the buffered raw data is used in the stage of the multi-stage decoding operation corresponding to the preliminary read-level voltage.

8. The machine-implemented method of claim 1 , wherein the plurality of memory cells are part of a block of a plurality of blocks on a die, and

wherein a respective decoding success indicator is maintained for the block, a group of blocks comprising the block, or the die.

9. A data storage system, comprising:

a non-volatile memory device; and

a controller configured to:

select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator;

execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells in the non-volatile memory device using the preliminary read-level voltage;

return decoded data from the preliminary hard decoding operation when the preliminary hard decoding operation is successful;

when the preliminary hard decoding operation is unsuccessful:

execute a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, wherein each stage of the multi-stage decoding operation comprises executing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read-level voltage from the sequence of read-level voltages corresponding to the stage, and wherein the stages of the multi-stage decoding operation are executed sequentially until one of the one or more decoding operations in one of the stages successfully decodes the raw data read from the plurality of memory cells; and

return decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and

maintain the decoding success indicator based on results of the preliminary hard decoding operation or the multi-stage decoding operation,

wherein when a first hard decoding operation using a first read-level voltage of the sequence of read-level voltages is unsuccessful, a next decoding operation that follows the first hard decoding operation is a first soft decoding operation regardless of whether a second hard decoding operation is available,

wherein the first soft decoding operation is associated with the first read-level voltage,

wherein when the first soft decoding operation is performed, the first soft decoding operation is performed without re-reading the plurality of memory cells,

wherein when the first soft decoding operation is unsuccessful, the first soft decoding operation is followed by a second soft decoding operation associated with the first read-level voltage,

wherein when the second soft decoding operation is performed, the second soft decoding operation is performed without re-reading the plurality of memory cells,

wherein the first hard decoding operation is (a) the preliminary hard decoding operation or (b) a hard decoding operation of the multi-stage decoding operation, and

wherein the first read-level voltage is (x) the preliminary read-level voltage or (y) the respective read-level voltage, from the sequence of read-level voltages, corresponding to the stage of the multi-stage decoding operation.

10. The data storage system of claim 9 , wherein the one or more decoding operations of each stage of the multi-stage decoding operation comprises a hard decoding operation and up to a plurality of soft decoding operations.

11. The data storage system of claim 10 , wherein the decoding success indicator indicates one read-level voltage of the sequence of read-level voltages, and

wherein the controller configured to maintain the decoding success indicator comprises the controller configured to set the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data.

12. The data storage system of claim 10 , wherein the controller is further configured to increment a counter value corresponding to the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data,

wherein the controller configured to maintain the decoding success indicator comprises the controller configured to set the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages with the highest corresponding counter value.

13. The data storage system of claim 12 , wherein the controller is further configured to maintain the decoding success indicator following completion of a number of read requests greater than one since the decoding success indicator was last maintained.

14. The data storage system of claim 10 , wherein the controller is further configured to:

buffer the raw data read from the plurality of memory cells using the preliminary read-level voltage,

wherein the buffered raw data is used in the stage of the multi-stage decoding operation corresponding to the preliminary read-level voltage.

15. The data storage system of claim 9 , wherein the plurality of memory cells are part of a block of a plurality of blocks on the non-volatile memory device, and

wherein the controller is further configured to maintain a respective decoding success indicator for the block, a group of blocks comprising the block, or the non-volatile memory device.

16. The data storage system of claim 9 , wherein:

each stage of the multi-stage decoding operation comprises one hard decoding operation followed by up to a plurality of soft decoding operations, and

when one respective read-level voltage of a given stage of the multi-stage decoding operation is same as the preliminary read-level voltage, the one hard decoding operation of the given stage is skipped.

17. A processor-readable medium encoded with executable instructions that, when executed by a processor, perform a method comprising:

selecting a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator;

executing a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage;

buffering the raw data read from the plurality of memory cells using the preliminary read-level voltage;

returning decoded data from the preliminary hard decoding operation when the preliminary hard decoding operation is successful;

when the preliminary hard decoding operation is unsuccessful:

executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, wherein the buffered raw data is used in a stage of the multi-stage decoding operation corresponding to the preliminary read-level voltage; and

returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and

maintaining the decoding success indicator based on results of the preliminary hard decoding operation or the multi-stage decoding operation,

wherein when a first hard decoding operation using a first read-level voltage of the sequence of read-level voltages is unsuccessful, a next decoding operation that follows the first hard decoding operation is a first soft decoding operation regardless of whether a second hard decoding operation is available,

wherein the first soft decoding operation is associated with the first read-level voltage,

wherein when the first soft decoding operation is performed, the first soft decoding operation is performed without re-reading the plurality of memory cells,

wherein when the first soft decoding operation is unsuccessful, the first soft decoding operation is followed by a second soft decoding operation associated with the first read-level voltage,

wherein when the second soft decoding operation is performed, the second soft decoding operation is performed without re-reading the plurality of memory cells,

wherein the first hard decoding operation is (a) the preliminary hard decoding operation or (b) a hard decoding operation of the multi-stage decoding operation, and

wherein the first read-level voltage is (x) the preliminary read-level voltage or (y) a respective read-level voltage, from the sequence of read-level voltages, corresponding to a stage of the multi-stage decoding operation.

18. The processor-readable medium of claim 17 , wherein each stage of the multi-stage decoding operation comprises executing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read-level voltage from the sequence of read-level voltages corresponding to the stage, and

wherein the stages of the multi-stage decoding operation are executed sequentially until one of the one or more decoding operations in one of the stages successfully decodes the raw data read from the plurality of memory cells.

19. The processor-readable medium of claim 18 , wherein the one or more decoding operations of each stage of the multi-stage decoding operation comprises a hard decoding operation and up to a plurality of soft decoding operations.

20. The processor-readable medium of claim 18 , wherein the decoding success indicator indicates one read-level voltage of the sequence of read-level voltages, and

wherein maintaining the decoding success indicator comprises setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data.

21. The processor-readable medium of claim 18 , wherein the method further comprises incrementing a counter value corresponding to the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data,

wherein maintaining the decoding success indicator comprises setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages with the highest corresponding counter value.

22. The processor-readable medium of claim 21 , wherein the decoding success indicator is maintained following completion of a number of read requests greater than one since the decoding success indicator was last maintained.

23. A data storage system comprising:

non-volatile memory;

means for selecting a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator;

means for executing a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage, and returning decoded data from the preliminary hard decoding operation when the preliminary hard decoding operation is successful;

means for executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the sequence of read-level voltages and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation when the preliminary hard decoding operation is unsuccessful; and

means for maintaining the decoding success indicator based on results of the preliminary hard decoding operation or the multi-stage decoding operation,

wherein when a first hard decoding operation using a first read-level voltage of the sequence of read-level voltages is unsuccessful, a next decoding operation that follows the first hard decoding operation is a first soft decoding operation regardless of whether a second hard decoding operation is available,

wherein the first soft decoding operation is associated with the first read-level voltage,

wherein when the first soft decoding operation is performed, the first soft decoding operation is performed without re-reading the plurality of memory cells,

wherein when the first soft decoding operation is unsuccessful, the first soft decoding operation is followed by a second soft decoding operation associated with the first read-level voltage,

wherein when the second soft decoding operation is performed, the second soft decoding operation is performed without re-reading the plurality of memory cells,

wherein the first hard decoding operation is (a) the preliminary hard decoding operation or (b) a hard decoding operation of the multi-stage decoding operation, and

wherein the first read-level voltage is (x) the preliminary read-level voltage or (y) a respective read-level voltage, from the sequence of read-level voltages, corresponding to a stage of the multi-stage decoding operation.

24. The data storage system of claim 23 , wherein each stage of the multi-stage decoding operation comprises executing a hard decoding operation and up to a plurality of soft decoding operations to decode raw data read from the plurality of memory cells using a respective read-level voltage from the sequence of read-level voltages corresponding to the stage, and

wherein the stages of the multi-stage decoding operation are configured to be executed sequentially until one of the hard decoding operation or the up to a plurality of soft decoding operations in one of the stages successfully decodes the raw data read from the plurality of memory cells.

25. The data storage system of claim 24 , comprising:

means for buffering the raw data read from the plurality of memory cells using the preliminary read-level voltage, wherein the buffered raw data is used in the stage of the multi-stage decoding operation corresponding to the preliminary read-level voltage,

wherein the decoding success indicator indicates one read-level voltage of the sequence of read-level voltages, and

wherein the means for maintaining the decoding success indicator comprises means for setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data.

26. The data storage system of claim 24 , further comprising means for incrementing a counter value corresponding to the read-level voltage from the sequence of read-level voltages used to read the successfully decoded raw data,

wherein the means for maintaining the decoding success indicator comprises means for setting the decoding success indicator to indicate the read-level voltage from the sequence of read-level voltages with the highest corresponding counter value following completion of a number of read requests greater than one since the decoding success indicator was last maintained.

Assignments (10)

Continuity (1)