Detecting a faulty memory block
View Patent ↗Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.
1. A storage system, configured to detect a faulty block in a memory array during operation of the storage system, comprising:
the memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
perform a read operation on a memory block of the memory array, the read operation generating a failed bit count;
determine the failed bit count is above a value associated with an overall failed bit count;
determine the failed bit count is above a threshold value, the threshold value based on an initial failed bit count; and
in response to the failed bit count being above the threshold value;
perform a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, and the confirmation process resulting is in erase pass or erase fail; and
mark the memory block for garbage collection in response to determining the confirmation process results in erase fail.
2. The storage system of claim 1 , wherein the controller is further configured to set the level of the erase cycle by modifying at least one selected from a group comprising: an erase voltage parameter, an erase verify parameter, and a number of bits ignored during the erase cycle.
3. The storage system of claim 1 , wherein the number of the consecutive erase cycles is determined based on at least one selected from a group comprising: a difference in value between the overall failed bit count and an initial failed bit count; a number of erase cycles performed on the memory system; and a result of a flash write.
4. The storage system of claim 1 , wherein the controller is further configured to, prior to performing the number of consecutive erase cycles, move data stored on the memory block to a different location in the memory system.
5. A storage system, configured to detect a faulty block in a memory array during operation of the storage system, comprising:
the memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
perform a read operation on a memory block of the memory array, the read operation generating a failed bit count;
determine the failed bit count is above a value associated with an overall failed bit count;
determine the failed bit count is above a threshold value;
in response to the failed bit count being above the threshold value;
perform a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, and the confirmation process resulting in erase pass or erase fail; and
mark the memory block for garbage collection in response to determining the confirmation process results in erase fail; and
update, based on the failed bit count, the value associated with the overall failed bit count, wherein the value associated with the overall failed bit count is a median failed bit count.
6. A method for detecting a faulty block in a memory system during operation of the memory system, comprising:
performing a read operation on a memory block, the read operation generating a failed bit count;
determining the failed bit count is above a threshold value; and
in response to the failed bit count being above the threshold value:
performing a confirmation process on the memory block, the confirmation process defining a level of an erase cycle, and the confirmation process resulting in erase pass or erase fail; and
marking the memory block for garbage collection in response to determining the confirmation process results in erase fail;
wherein the number of the consecutive erase cycles is determined based on at least one selected from a group comprising: a different in value between the overall failed bit count and an initial failed bit count; a number of erase cycles performed on the memory system; and a result of a flash write.
7. The method of claim 6 , further comprising setting the level of the erase cycle by modifying at least one selected from a group comprising: an erase voltage parameters; an erase verify parameter; and a number of bits ignored during the erase cycle.
8. The method of claim 6 , further comprising, prior to the performing the confirmation process, moving data stored on the memory block to a different location in the memory system.
9. The method of claim 6 , further comprising determining the failed bit count is above a median failed bit count.
10. The method of claim 6 , further comprising:
performing a second read operation on a second memory block, the second read operation generating a second failed bit count;
determining, the second failed bit count is above a second value associated with an overall failed bit count;
determining the second failed bit count is above a second threshold value; and
in response to the second failed bit count being above the second threshold value:
performing the confirmation on the second memory block; and
refraining from marking the second memory block for garbage collection, in response to determining the confirmation process results in erase pass.
11. A memory controller, comprising:
a first terminal configured to couple to a memory array,
the memory controller configured to:
perform a read operation on a memory block, the read operation generating a failed bit count;
determine the failed bit count is above a threshold value; and
in response to the failed bit count being above the threshold value:
perform a confirmation process on the memory block, the confirmation process defining a level of an erase cycle, and the confirmation process resulting in erase pass or erase fail; and
mark the memory block for garbage collection in response to determining the confirmation process results in erase fail;
wherein the level of the erase cycle is determined based on at least one selected from a group comprising: a difference in value between the overall failed bit count and an initial failed bit count; a number of program and erase cycles performed on the memory system; and a result of a flash write.
12. The memory controller of claim 11 , further configured to set the level of the erase cycle by modifying at least one selected from a group comprising: an erase voltage parameter, an erase verify parameter, and a number of bits ignored during the erase cycle.
13. The memory controller of claim 11 , further configured to determine the failed bit count is above a median failed bit count.
14. The memory controller of claim 11 , further configured to, prior to performing the confirmation process, move data stored on the memory block to a different location in the memory array.
15. The memory controller of claim 11 , further configured to:
perform, a second read operation on a second memory block, the second read operation generating a second failed bit count;
determine the second failed bit count is above a second median failed bit count;
determine the second failed bit count is above a second threshold value; and
in response to the second failed bit count being above the second threshold value:
perform the confirmation process on the second memory block; and
operate the second memory block using normal operating conditions, in response to a determination that the confirmation process results in erase pass.
16. The memory controller of claim 11 , wherein when the memory controller performs the confirmation process, the memory controller further, performs a number of consecutive erase cycles on the memory block.