Channel pre-charge process for memory devices using hole pre-charge operation
The memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. During the hole pre-charge operation, the circuitry applies a positive CELSRC pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.
1 . A method of programming a memory device, comprising the steps of:
preparing a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels;
pre-charging a plurality of channels in a memory device using a hole pre-charge operation, the hole pre-charge operation including the steps of:
applying a positive source line pre-charge voltage to a source line of the memory block,
applying a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes, and
wherein a difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is at least six Volts.
2 . The method as set forth in claim 1 , wherein the difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is approximately seven Volts.
3 . The method as set forth in claim 1 , further including the step of applying a programming voltage to the selected word line after the pre-charge operation is completed.
4 . The method as set forth in claim 1 , further including the steps of ramping the source line down from the source line pre-charge voltage and ramping the unselected word lines up from the unselected word line pre-charge voltage.
5 . The method as set forth in claim 4 , wherein the step of ramping the source line down from the source line pre-charge voltage occurs prior to the step of ramping the unselected word lines up from the unselected word line pre-charge voltage.
6 . The method as set forth in claim 1 , wherein the negative unselected word line pre-charge voltage is between negative two and negative four Volts.
7 . The method as set forth in claim 1 , wherein the positive source line pre-charge voltage is between three and five Volts.
8 . A memory device, comprising:
a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels;
circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels, the hole pre-charge operation including:
applying a positive source line pre-charge voltage to a source line of the memory block,
applying a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes, and
wherein a difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is at least six Volts.
9 . The memory device as set forth in claim 8 , wherein the difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is approximately seven Volts.
10 . The memory device as set forth in claim 8 , wherein the circuitry is further configured to apply a programming voltage to the selected word line after the pre-charge operation is completed.
11 . The memory device as set forth in claim 8 , wherein the circuitry is further configured to ramp the source line down from the source line pre-charge voltage and ramp the unselected word lines up from the unselected word line pre-charge voltage.
12 . The memory device as set forth in claim 11 , wherein the circuitry is configured to ramp the source line down from the source line pre-charge voltage prior to ramping the unselected word lines up from the unselected word line pre-charge voltage.
13 . The memory device as set forth in claim 8 , wherein the negative unselected word line pre-charge voltage is between negative two and negative four Volts.
14 . The memory device as set forth in claim 8 , wherein the positive source line pre-charge voltage is between three and five Volts.
15 . An apparatus, comprising:
a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels;
a programming means that is configured to program the memory cells of a selected word line of the plurality of word lines in a programming operation, the programming operation including:
in a hole pre-charge operation, applying a positive source line pre-charge voltage to a source line of the memory block, and applying a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes,
after the pre-charge operation, applying a programming voltage to the selected word line to program at least one of the memory cells in the selected word line, and
wherein a difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is at least six Volts.
16 . The apparatus as set forth in claim 15 , wherein the difference between the source line pre-charge voltage and the unselected word line pre-charge voltage is approximately seven Volts.
17 . The apparatus as set forth in claim 15 , wherein the programming means is configured to ramp the source line down from the source line pre-charge voltage prior to ramping the unselected word lines up from the unselected word line pre-charge voltage.