Granted Patent B2

US 9,251,899 · App. 12/369,733 · Granted Feb 2, 2016

Abstract

Claims (45)

1. A method comprising:

providing a two dimensional array of memory modules in a system, the two dimensional array of memory modules including

non-volatile memory in a plurality of memory slices, and

a plurality of slave memory controllers respectively coupled to the non-volatile memory in the plurality of memory slices;

providing a master memory controller coupled between one or more processors and the two dimensional array of memory modules;

combining a plurality of block memory requests into a compound memory request to read data from or write data into the non-volatile memory in the plurality of memory slices; and

in response to the compound memory request, buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.

2. The method of claim 1 , further comprising:

aggregating data from the one or more processors together in response to the compound memory request to write data into the memory in the plurality of memory slices.

3. The method of claim 1 , further comprising:

aggregating data together from memory in the plurality of memory slices in response to the compound memory request to read data from the memory in the plurality of memory slices.

4. The method of claim 1 , wherein each of the memory modules further includes

an address controller coupled to the plurality of slave memory controllers and the master memory controller, the address controller receiving addresses from the master memory controller and the address controller generating addresses and control signals for the plurality of slave memory controllers in response to the addresses from the master memory controller.

5. The method of claim 1 , wherein the master memory controller includes a two-dimensional transpositional buffer and the master memory controller buffers and transposes data by

reading data from the two dimensional array of memory modules,

writing the data in a two-dimensional transpositional buffer row by row, and

reading out the data column by column from the two-dimensional transpositional buffer to provide the data to the one or more processors.

6. The method of claim 1 , wherein the master memory controller includes a two-dimensional transpositional buffer and the master memory controller buffers and transposes data by

receiving data from the one or more processors,

writing the data into the two-dimensional transpositional buffer column by column, and

reading out the data from the two-dimensional transpositional buffer row by row to write the data into the two-dimensional array of memory modules.

7. A method for a pre-existing computer system, the method comprising:

upgrading the pre-existing computer system including

plugging a plurality of memory modules into a plurality of memory module sockets to form a dimensional array of memory modules, each including

a plurality of non-volatile memory integrated circuits arranged into a plurality of memory column slices and a plurality of rows, and

a plurality of slave memory controllers respectively coupled to the non-volatile memory integrated circuits in the plurality of memory slices;

upgrading a pre-existing memory controller to a master memory controller coupled between one or more processors and the two dimensional array of memory modules;

wherein the plurality of non-volatile memory integrated circuits arranged into the plurality of memory slices and the plurality of rows are selectively activated by the master memory controller in two dimensions over the two dimensional memory array of modules; and

wherein, in response to a compound memory request, the master memory controller buffers and transposes data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.

8. The method of claim 7 , further comprising:

prior to plugging the two-dimensional array of memory modules into the memory module sockets, removing a plurality of dynamic random access memory modules from the memory sockets.

9. The method of claim 7 , wherein

the pre-existing memory controller is upgraded to a master memory controller by a master memory controller software driver.

10. The method of claim 7 , wherein

the pre-existing memory controller is upgraded to a master memory controller by plugging a packaged master memory controller integrated circuit into a socket, the socket coupled to the one or more processors and the two-dimensional array of memory modules by printed circuit board traces.

11. The method of claim 7 , wherein each of the memory modules further includes

an address controller coupled to the plurality of slave memory controllers and the master memory controller, the address controller receiving addresses from the master memory controller and the address controller generating addresses and control signals for the plurality of slave memory controllers in response to the addresses from the master memory controller.

12. The method of claim 7 , wherein the master memory controller includes a two-dimensional transpositional buffer and the master memory controller buffers and transposes data by

reading data from the two-dimensional array of memory modules,

writing the data in a two-dimensional transpositional buffer row by row, and

reading out the data column by column from the two-dimensional transpositional buffer to provide the data to the one or more processors.

13. The method of claim 7 , wherein the master memory controller includes a two-dimensional transpositional buffer and the master memory controller buffers and transposes data by

receiving data from the one or more processors,

writing the data into a two-dimensional transpositional buffer column by column, and

reading out the data from the two-dimensional transpositional buffer row by row to write the data into the two-dimensional array of memory modules.

Assignments (11)