IP Library Granted Patent US 11,422,828
Granted Patent B2
US 11,422,828 · App. 17/094,686 · Granted Aug 23, 2022

Interleaved host reset and next re-initialization operations

Inventor: Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F9/4411G06F13/1668
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Quick Facts
Patent No.
US 11,422,828
App. No.
17/094,686
Granted
Aug 23, 2022
Kind
B2
Abstract

Embodiments of the present disclosure seek to mitigate the timing issues of prior approaches by performing the NVMe device reset and post-reset re-initialization in parallel. In embodiments, the NVMe device reset and re-initialization operations are logically divided into front-end and back-end operations that may be carried out in parallel. Upon receipt of the command from a host to reset, the NVMe device carries out front-end reset operations for resetting the device, and in parallel performing back-end reinitialization operations. Once the front-end reset operations are complete, or after a predetermined period of time, the NVMe device reports to the host that the device reset is complete, while back-end operations continue. Once all reset and reinitialization operations are complete, the NVMe device may continue to conduct I/O instructions from the host.

Claims (28)

1. A data storage device, comprising:

a controller comprising instructions that, when executed by a processor, cause the controller to perform a method of resetting the data storage device, the method comprising:

performing a set of front-end reset tasks and a set of back-end reset tasks in parallel upon receipt of a reset command;

transmitting a reset complete signal to a host system upon completion of the set of front-end reset tasks;

receiving a command from the host system; and

executing the command when the set of back-end reset tasks are complete.

2. The data storage device of claim 1 , wherein the set of back-end reset tasks are not complete when the reset complete signal is transmitted.

3. The data storage device of claim 1 , further comprising re-initialization of the storage device by the host system after transmitting the reset complete signal to the host system.

4. The data storage device of claim 1 , wherein a storage device ready signal is transmitted to the host system after a delay time.

5. The data storage device of claim 4 , wherein the delay time comprises estimating with a processor, a time to complete one of the front-end reset tasks and the back-end reset tasks.

6. The data storage device of claim 5 , wherein the delay time comprises estimating with a processor, a time to complete both of the front-end reset tasks and back-end reset tasks.

7. The data storage device of claim 1 , wherein the set of front-end reset tasks comprises one of resetting a register and resetting a queue, and the set of back-end reset tasks comprises writing to one of a NAND and a memory.

8. A data storage system, comprising:

a reset handler module configured to logically separate a front-end module from a back-end module, wherein front-end reset operations and back-end reset operations are carried out in parallel, and wherein the reset handler module configured to communicate with a host that reset operations are complete upon completion of front-end reset operations.

9. The data storage system of claim 8 , further comprising a reset handler evaluation module configured to determine a reset-complete notification time to provide to a host.

10. The data storage system of claim 9 , wherein the reset-complete notification time is determined to be less than the time required to carry out back-end reset operations.

11. The data storage system of claim 9 , wherein the reset-complete notification time is less than the time required to carry out back-end reset operations and front-end reset operations.

12. The data storage system of claim 9 , wherein the reset handler evaluation module is configured to determine the reset-complete notification time based at least on part on the completion of one of the front-end reset operations and back-end reset operations.

13. The data storage system of claim 9 , wherein the reset handler evaluation module is configured to determine the reset-complete notification time based at least in part on the completion of both of the front-end reset operations and back-end reset operations.

14. The data storage system of claim 11 , wherein at least one of the front-end reset operations used to determine the reset-complete notification time is pending activities in the data storage system at a time reset instructions are received from the host.

15. The data storage system of claim 8 , wherein the reset handler module communicates with a host that reset operations are complete prior to the completion of back-end reset operations.

16. The data storage system of claim 15 , wherein the data storage system is configured to provide doorbell access to the host prior to the completion of back-end reset operations.

17. The data storage system of claim 16 , wherein the data storage system is configured to not fetch commands from the host until back-end reset operations are complete.

18. A data storage system, comprising:

means for logically separating front-end reset operations from back-end reset operations; and

means for executing the front-end reset operations and back-end reset operations in parallel.

19. The data storage system of claim 18 , further comprising means for notifying a host that at least one of the front-end reset operations and back-end reset operations is complete.

20. The data storage system of claim 19 , configured such that one of the front-end reset operations and back-end reset operations is not complete after notifying the host.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 055404 FRAME 0942 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0407 →
SECURITY INTEREST Recorded Feb 24, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 055404/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2020
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 054331/0695 →