Memory matched low density parity check coding schemes
Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.
1. A memory controller, comprising:
a memory interface configured to interface with a non-volatile memory; and
a controller configured to: receive a plurality of data pages associated with a write command, the plurality of data pages to be stored in the non-volatile memory, wherein the plurality of data pages is N data pages,
transform the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2 N −1 data pages,
determine a plurality of parity bits based on the plurality of transformed data pages, and
store the plurality of data pages and the plurality of parity bits in the non-volatile memory.
2. The memory controller of claim 1 , wherein each of the plurality of transformed data pages is affected by errors of an associated read threshold of the non-volatile memory.
3. The memory controller of claim 1 , wherein a bit error rate of the plurality of data pages is equal to a bit error rate of the plurality of transformed data pages.
4. The memory controller of claim 1 , wherein the non-volatile memory includes a plurality of memory cell states, and wherein a number of the plurality of transformed data pages is based on a number of read thresholds of the plurality of memory cell states.
5. The memory controller of claim 1 , wherein the controller is further configured to:
retrieve the stored plurality of data pages and the stored plurality of parity bits from the non-volatile memory, the stored plurality of data pages including a plurality of data hard bits and a plurality of data soft bits, and the stored plurality of parity bits including a plurality of parity hard bits and a plurality of parity soft bits.
6. The memory controller of claim 5 , wherein the controller is further configured to:
transform the stored plurality of data pages into a second plurality of transformed data pages, and
determine log likelihood ratio estimations for the second plurality of transformed data pages and the plurality of party bits.
7. The memory controller of claim 6 , wherein the controller is further configured to:
generate a corrected plurality of data pages based on the log likelihood ratio estimations for the second plurality of transformed data pages and the log likelihood ratio estimations for the plurality of parity bits.
8. The memory controller of claim 5 , wherein the controller is further configured to:
transform the stored plurality of data pages into a second plurality of transformed data pages,
determine whether the second plurality of transformed data pages and the plurality of parity bits satisfy a set of parity check constraints, and
adjust, in response to the second plurality of transformed data pages and the plurality of parity bits failing to satisfy the set of parity check constraints, a value of at least one of the second plurality of transformed data pages.
9. The memory controller of claim 8 , wherein the controller is further configured to:
determine whether the second plurality of transformed data pages and the plurality of parity bits satisfy the set of parity check constraints, and
adjust the value of at least one of the second plurality of transformed data pages until the second plurality of transformed data pages and the plurality of parity bits satisfy the set of parity check constraints.
10. The memory controller of claim 1 , wherein a bit error distribution induced by the non-volatile memory over the plurality of transformed data pages is different than an error distribution over the plurality of data pages.
11. The memory controller of claim 1 , wherein the controller is further configured to:
determine a memory error model of the non-volatile memory based on an estimated bit error rate of the plurality of transformed data pages, and
determine a health of the non-volatile memory based on the memory error model.
12. The memory controller of claim 1 , wherein the controller is further configured to:
adjust read thresholds of the non-volatile memory based on an estimated bit error rate of the plurality of transformed data pages.
13. A method comprising:
receiving a plurality of data pages associated with a write command, the plurality of data pages to be stored in a non-volatile memory, wherein the plurality of data pages is N data pages,
transforming the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2 N −1 data pages,
determining a plurality of parity bits based on the plurality of transformed data pages, and
storing the plurality of data pages and the plurality of parity bits in the non-volatile memory.
14. The method of claim 13 , wherein N is four.
15. The method of claim 13 , wherein a bit error rate of the plurality of data pages is equal to a bit error rate of the plurality of transformed data pages.
16. The method of claim 13 , wherein the non-volatile memory includes a plurality of memory cell states, and wherein a number of the plurality of transformed data pages is based on a number of the plurality of memory cell states.
17. The method of claim 13 , further comprising:
retrieving the stored plurality of data pages and the stored plurality of parity bits from the non-volatile memory, the stored plurality of data pages including a plurality of data hard bits and a plurality of data soft bits, and the stored plurality of parity bits including a plurality of parity hard bits and a plurality of parity soft bits.
18. The method of claim 17 , further comprising:
transforming the stored plurality of data pages into a second plurality of transformed data pages, and
determining log likelihood ratio estimations for the second plurality of transformed data pages and the plurality of party bits.
19. The method of claim 18 , further comprising:
generating a corrected plurality of data pages based on the log likelihood ratio estimations for the second plurality of transformed data pages and the log likelihood ratio estimations for the plurality of parity bits.
20. An apparatus comprising:
means for interfacing with a non-volatile memory;
means for receiving a plurality of data pages associated with a write command, the plurality of data pages to be stored in the non-volatile memory, wherein the plurality of data pages is N data pages,
means for transforming the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the transformed data pages is 2 N −1 data pages,
means for determining a plurality of parity bits based on the plurality of transformed data pages, and
means for storing the plurality of data pages and the plurality of parity bits in the non-volatile memory.