IP Library Granted Patent US 9,251,061
Granted Patent B2
US 9,251,061 · App. 14/016,218 · Granted Feb 2, 2016

Methods for accessing memory in a two-dimensional main memory having a plurality of memory slices

Inventors: Vijay Karamcheti (Los Altos, CA); Kumar Ganapathy (Los Altos, CA)
Assignee: Virident Systems, Inc.
G06F12/0246G11C5/04G11C29/76
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Quick Facts
Patent No.
US 9,251,061
App. No.
14/016,218
Granted
Feb 2, 2016
Kind
B2
Abstract

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Claims (48)

1. A method for accessing memory in a two-dimensional main memory having a plurality of memory slices, the method comprising:

receiving a plurality of block memory requests to access a main memory having a plurality of memory slices, wherein each memory slice includes a portion of memory of a plurality of memory modules in the two-dimensional main memory;

combining the plurality of block memory requests into a compound memory request that can concurrently access data in different memory slices over a plurality of memory modules in the two-dimensional main memory;

aggregating data together in response to the compound memory request; and

transposing data between rows of data for the main memory and columns of data for one or more processors in response to the plurality of block memory requests.

2. The method of claim 1 , wherein

the compound memory request is a write request, and

memory block data is aggregated and transposed into a row of data to write into the plurality of memory slices in the main memory.

3. The method of claim 2 , further comprising:

activating the plurality of memory slices within a two-dimensional array of memory modules in the main memory to write the row of data into memory devices of selectively activated memory modules.

4. The method of claim 2 , wherein

the transposing of data includes

storing data from the one or more processors by column into a transpositional buffer, and

reading data out from the transpositional buffer by row for writing into the main memory.

5. The method of claim 1 , wherein

the compound memory request is a read request, and

memory block data is aggregated together from the plurality of memory slices to read a row of data and transposed to provide the data to the one or more processors.

6. The method of claim 5 , further comprising:

activating the plurality of memory slices within a two-dimensional array of memory modules in the main memory to read the row of data out from memory devices of selectively activated memory modules.

7. The method of claim 5 , wherein

the transposing of data includes

storing data from main memory by row into a transpositional buffer, and

reading data out from the transpositional buffer by column for the one or more processors.

8. A method for reading data out of a two-dimensional main memory having a plurality of memory slices, the method comprising:

receiving a plurality of block memory read requests to access a main memory having a plurality of memory slices, wherein each memory slice includes a portion of memory of a plurality of memory modules in the two-dimensional main memory;

combining the plurality of block memory read requests into a compound memory slice request, wherein the compound memory slice request is a read request that can concurrently access data in different memory slices over a plurality of memory modules in the two-dimensional main memory;

executing the compound memory slice request with the main memory, wherein memory block data is aggregated together from the plurality of memory slices to read out a row of data in response to the compound memory slice request;

transposing rows of data from the main memory into columns of data for one or more processors; and

providing a row of data to the one or more processors to process data.

9. The method of claim 8 , further comprising:

activating the plurality of memory slices within a two-dimensional array of memory modules in the main memory to read the row of data out from memory devices of selectively activated memory modules.

10. The method of claim 8 , wherein

the transposing of rows of data includes

storing data from main memory by row into a transpositional buffer, and

reading data out from the transpositional buffer by column for the one or more processors.

11. A method for writing data into a two-dimensional main memory having a plurality of memory slices, the method comprising:

receiving a plurality of block memory write requests to access a main memory having a plurality of memory slices, wherein each memory slice includes a portion of memory of a plurality of memory modules in the two-dimensional main memory;

combining the plurality of block memory write requests into a compound memory slice request, wherein the compound memory slice request is a write request that can concurrently access data in different memory slices over a plurality of memory modules in the two-dimensional main memory;

aggregating memory block data together associated with the plurality of block memory write requests of the compound memory slice request;

executing the compound memory slice request with the main memory;

transposing columns of data associated with the compound memory slice request into a row of data to write into the plurality of memory slices in the main memory; and

providing the row of data to the plurality of memory slices for storage in the main memory.

12. The method of claim 11 , further comprising:

activating the plurality of memory slices within a two-dimensional array of memory modules in the main memory to write the row of data into memory devices of selectively activated memory modules.

13. The method of claim 11 , wherein

the transposing of columns of data includes

storing data from the one or more processors by column into a transpositional buffer, and

reading data out from the transpositional buffer by row for writing into the main memory.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020
From: VIRIDENT SYSTEMS, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053180/0472 →
CHANGE OF NAME Recorded Jan 30, 2019
From: VIRIDENT SYSTEMS, INC
To: VIRIDENT SYSTEMS, LLC
Reel/Frame 048196/0580 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2013
From: KARAMCHETI, VIJAY; GANAPATHY, KUMAR
To: VIRIDENT SYSTEMS, INC.
Reel/Frame 031188/0642 →
Continuity (3)
Division 12369728 · Feb 11, 2009
Provisional Application 61028183 · Feb 12, 2008
Related Publication 20140075101A1 · Mar 13, 2014