Toggle mode (™) coding with circuit bounded array memory
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.
1 . A data storage device, comprising:
a memory device comprising a plurality of complementary metal oxide semiconductor (CMOS) chips and a plurality of memory dies, wherein each CMOS chip of the plurality of CMOS chips are coupled to one or more memory dies of the plurality of memory dies; and
a controller coupled to the memory device, wherein the controller is configured to:
dynamically calibrate a toggle mode (TM) encoder of the controller, wherein dynamically calibrating the TM encoder of the controller optimizes and reduces an average power usage over a transmission line from the controller to a CMOS chip; and
transfer encoded data from the controller to the memory device; wherein each CMOS chip of the plurality of CMOS chips is configured to:
dynamically calibrate a TM encoder of a CMOS chip coupled to a memory die; and
transfer encoded data from the memory die to the controller based on the dynamically calibrated TM encoder of the CMOS chip.
2 . The data storage device of claim 1 , wherein dynamically calibrating the TM encoder of the controller comprises causing the TM encoder of the controller to decrease a number of switches from 1-bits to 0-bits while encoding the data.
3 . The data storage device of claim 1 , wherein dynamically calibrating the TM encoder of the controller comprises causing the TM encoder of the controller to decrease a number of switches from 0-bits to 1-bits while encoding the data.
4 . The data storage device of claim 1 , wherein dynamically calibrating the TM encoder of the CMOS chip comprises causing the TM encoder of the CMOS chip to decrease a number of switches from 1-bits to 0-bits while encoding the data.
5 . The data storage device of claim 1 , wherein dynamically calibrating the TM encoder of the CMOS chip comprises causing the TM encoder of the CMOS chip to decrease a number of switches from 0-bits to 1-bits while encoding the data.
6 . The data storage device of claim 1 , wherein dynamically calibrating of the TM encoder of the controller or the TM encoder of the CMOS chip comprises causing the TM encoder of the controller or the TM encoder of the CMOS chip to flip a number of 0-bits to 1-bits transmitted over the transmission line.
7 . The data storage device of claim 6 , wherein the flipping a number of 0-bits to 1-bits over the transmission line is in response to pseudo open drain (POD) interfaces that have a termination coupled to a voltage common collector (Vcc).
8 . The data storage device of claim 1 , wherein dynamically calibrating of the TM encoder of the controller or the TM encoder of the CMOS chip comprises causing the TM encoder of the controller or the TM encoder of the CMOS chip to flip a number of 1-bits to 0-bits transmitted over the transmission line.
9 . The data storage device of claim 8 , wherein the flipping a number of 0-bits to 1-bits over the transmission line is in response to low voltage swing termination logic (LVSTL) interfaces that have a termination coupled to a ground.
10 . The data storage device of claim 1 , wherein dynamically calibrating of the TM encoder of the controller or the TM encoder of the CMOS chip comprises causing the TM encoder of the controller or the TM encoder of the CMOS chip to reduce an amount of polarity switching of 1-bits to 0-bits or 0-bits to 1-bits between adjacent transmission lines.
11 . A data storage device, comprising:
a memory device comprising a plurality of complementary metal oxide semiconductor (CMOS) chips and a plurality of memory dies, wherein each CMOS chip of the plurality of CMOS chips are coupled to one or more memory dies of the plurality of memory dies; and
a controller coupled to the memory device, wherein the controller is configured to:
toggle mode (TM) encode data being sent to the memory device, wherein the TM encoding data being sent to the memory device comprises changing a number of bits of the data from 1-bits to 0-bits or from 0-bits to 1-bits based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line;
wherein a CMOS chip of the plurality of CMOS chips is configured to:
toggle mode (TM) encode data being sent to the controller from a coupled memory die, wherein the TM encoding data being sent to the controller comprises changing a number of bits of the data from 1-bits to 0-bits or from 0-bits to 1-bits based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line.
12 . The data storage device of claim 11 , wherein the analysis of the interface transmission line comprises determining an amount of polarity switching between adjacent transmission lines.
13 . The data storage device of claim 11 , wherein the analysis of the interface transmission line determining whether the interface transmission line terminates at a voltage common collector (VCC) or at a ground.
14 . The data storage device of claim 13 , wherein the TM encoding, by the controller or the CMOS chip, comprises changing the number of bits of the data from 0-bits to 1-bits when the interface transmission line terminates at the VCC, and wherein a number of 1-bits is greater than a number of 0-bits.
15 . The data storage device of claim 13 , wherein the TM encoding, by the controller or the CMOS chip, comprises changing the number of bits of the data from 1-bits to 0-bits when the interface transmission line terminates at the ground, and wherein a number of 0-bits is greater than a number of 1-bits.
16 . The data storage device of claim 11 , wherein the CMOS chip is either:
circuit bounded array (CBA);
circuit under array (CuA); or
circuit above array (CAA).
17 . The data storage device of claim 11 , wherein the controller comprises a first TM encoder configured to TM encode the data being sent to the memory device, and wherein the CMOS chip comprises a second TM encoder configured to TM encode the data being sent to the controller from the coupled memory die.
18 . The data storage device of claim 17 , wherein the TM encoding by the first TM encoder is different than the TM encoding by the second TM encoder.
19 . A data storage device, comprising:
memory means configured to:
toggle mode (TM) encode data to send to a controller coupled to the memory means, wherein TM encoding data to send to the controller coupled to the memory means comprises dynamically calibrating a TM encoder of the memory means to optimize and reduce an average power usage over a transmission line from the memory means to the controller coupled to the memory means; and
the controller coupled to the memory means, wherein the controller is configured to:
toggle mode (TM) encode data to send to the memory means, wherein TM encoding data to send to the memory means comprises dynamically calibrating a TM encoder of the controller to optimize and reduce an average power usage over a transmission line from the controller to the memory means.
20 . The data storage device of claim 19 , wherein TM encoding data to send to the controller and TM encoding data to send to the memory means comprises switching 1-bits to 0-bits or 0-bits to 1-bits based on:
reducing an amount of switching of bits from 1-bits to 0-bits or 0-bits to 1-bits;
reducing an amount of polarity switching between adjacent transmission lines; and
reducing an amount of direct current (DC) power spent on terminations by shifting bit distribution of 1-bits and 0-bits based on whether the termination is at a voltage common collector or at a ground.