Toggle mode (TM) coding with circuit bounded array memory
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises a first toggle mode (TM) encoder and a first TM decoder, wherein the first TM encoder and the first TM decoder are calibrated based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line, and wherein the controller is configured to:
receive a command to write data to the memory device;
perform TM encoding on the write data using the first TM encoder; and
send the TM encoded write data to the memory device;
wherein the memory device comprises a plurality of second TM encoders and a plurality of second TM decoders, wherein a second TM encoder of the plurality of second TM encoders and a second TM decoder of the plurality second TM decoders are coupled to each memory die of the memory device, wherein the second TM encoder and the second TM decoder are calibrated based on the analysis of the interface transmission line and the one or more parasitic elements of the interface transmission line, and wherein the memory device is configured to:
receive the TM encoded write data;
decode the TM encoded write data received from the controller using the second TM decoder; and
write the decoded data to a location within the memory device.
2. The data storage device of claim 1 , wherein the memory device comprises a control circuit chip, wherein the control circuit chip comprises the second TM encoder and the second TM decoder.
3. The data storage device of claim 2 , wherein the control circuit chip is bonded to a memory die of the memory device.
4. The data storage device of claim 2 , wherein the control circuit chip comprises logic configured to perform TM decoding on the write data.
5. The data storage device of claim 1 , wherein the controller is further configured to:
receive TM encoded read data from the memory device; and
decode the TM encoded read data received from the memory device using the first TM decoder.
6. The data storage device of claim 5 , wherein the memory device is further configured to:
TM encode data read from the memory device using the one or more second TM encoders; and
send the TM encoded read data to the controller.
7. The data storage device of claim 6 , wherein the TM encoding performed at the controller and the TM encoding performed at the memory device are asymmetric.
8. The data storage device of claim 6 , wherein the TM encoding performed at the controller and the TM encoding performed at the memory device are symmetric.
9. The data storage device of claim 1 , further comprising a bus between the memory device and the controller for passing the TM encoded read and write data therebetween.
10. A data storage device, comprising:
a memory device, wherein the memory device comprises a plurality of second toggle mode (TM) encoders and a plurality of second TM decoders, wherein a second TM encoder of the plurality of second TM encoders and a second TM decoder of the plurality second TM decoders is coupled to each memory die of the memory device, wherein the second TM encoder and the second TM decoder are calibrated based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line, and wherein the memory device is configured to:
receive a read command to read data from a location within the memory device;
read the data;
TM encode the read data using the one or more second TM encoders; and
transmit the TM encoded read data; and
a controller coupled to the memory device, wherein the controller comprises a first TM encoder and a first TM decoder, wherein the first TM encoder and the first TM decoder are calibrated based on the analysis of the interface transmission line and the one or more parasitic elements of the interface transmission line, and wherein the controller is configured to:
receive the transmitted TM encoded read data;
decode the TM encoded read data received from the memory device using the first TM decoder; and
send the decoded data to a host device.
11. The data storage device of claim 10 , wherein the memory device comprises a control chip containing logic to perform the TM encoding.
12. The data storage device of claim 11 , wherein the control chip additionally comprises logic to perform TM decoding.
13. The data storage device of claim 10 , wherein the controller comprises logic to perform the TM decoding and logic to perform TM encoding.
14. The data storage device of claim 13 , wherein the TM encoding performed by the controller is different from the TM encoding performed by the memory device.
15. The data storage device of claim 10 , wherein the memory device is configured to receive TM encoded data, decode the TM encoded data, and write decoded data to a location in the memory device.
16. The data storage device of claim 10 , wherein the controller is configured to receive a write request for data, TM encode the write data, and send the TM encoded write data to the memory device.
17. The data storage device of claim 10 , wherein data sent from the controller to the memory device and data received at the controller from the memory device is TM encoded.
18. A data storage device, comprising:
a memory means configured to:
toggle mode (TM) decode data received; and
TM encode data read from the memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
decode TM encoded data received from the memory means, wherein the decoding TM encoded data received from the memory means is different than TM decoding data received at the memory means, and wherein the decoding TM encoded data received from the memory means and the TM decoding data received at the memory means are each based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line; and
TM encode write data to send to the memory means, wherein the TM encoding write data to send to the memory means is different than TM encoding data read from the memory means, and wherein the TM encoding write data to send to the memory means and the TM encoding data read from the memory means are each based on an analysis of an interface transmission line and one or more parasitic elements of the interface transmission line.
19. The data storage device of claim 18 , wherein the memory means comprises a memory die having a control circuit die bonded thereto.
20. The data storage device of claim 19 , wherein the control circuit die is configured to read decoded data from the memory die and write decoded data to the memory die.