Neural network data updates using in-place bit-addressable writes within storage class memory
Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.
1. A device, comprising:
a non-volatile memory (NVM) array configured for bit-addressable writes; and
processing circuitry configured to:
determine whether or not to pre-set a portion of memory within the NVM array to a first memory state before updating data stored within the NVM array, wherein the determination is based on an amount of change in the data to be updated;
in response to a determination to pre-set the portion of memory, pre-set the portion of memory to the first memory state and then change only particular bits within the pre-set portion to a second memory state using bit-addressable writes to update the data; and
in response to a determination to not pre-set the portion of memory, update the data by performing bit-addressable writes to update only particular bits of the stored data that need updating.
2. The device of claim 1 , wherein the NVM array is configured to perform bit-addressable writes by (a) applying a set pulse to change bits to the first memory state from the second memory state and (b) applying a re-set pulse to change bits to the second memory state from the first memory state, where the set pulse takes longer than the re-set pulse to change the state of a bit.
3. The device of claim 2 , wherein the processing circuitry is further configured, in response to a determination to pre-set the portion of memory, to:
pre-set all of the bit states of the portion of the NVM array to the first memory state by applying the set pulse to each bit within the portion of the NVM array; and
change selected bits from the first memory state to the second memory state to encode updated data in the NVM array by applying the re-set pulses to the selected bits.
4. The device of claim 1 , wherein the processing circuitry is further configured to determine whether or not to pre-set the portion of memory within the NVM by comparing the amount of change in the data to be updated against a threshold, and to then pre-set the portion of memory if the amount is at or above the threshold.
5. The device of claim 4 , wherein the processing circuitry is further configured to determine the amount of change in the data to be updated by one or more of predicting or estimating the amount of change in the data to be updated.
6. The device of claim 4 , wherein the data to be updated is generated from a multidimensional computation procedure and the processing circuitry is further configured to determine the amount of change in the data to be updated based on a current state of the multidimensional computation procedure.
7. The device of claim 6 , wherein the multidimensional computation procedure is a neural network computation procedure and the processing circuitry is further configured to determine the amount of change in the data to be updated based on a factor derived from a current learning rate of the neural network computation procedure.
8. The device of claim 7 , wherein the processing circuitry is further configured to repeat the determination at least once every iteration of the neural network computation procedure.
9. The device of claim 6 , wherein the processing circuitry is further configured to regularize the data by selectively disabling the updating of the data.
10. The device of claim 6 , wherein the processing circuitry is further configured to regularize the data by applying updates to only a portion of the data to be updated.
11. The device of claim 1 , wherein the NVM array comprises one of more of a phase-change memory (PCM) array, a magneto-resistive random access memory (MRAM) array, a resistive random access memory (ReRAM) array, and a three-dimensional cross-point (3D XPOINT) array.
12. A method for use by a device that includes a non-volatile memory (NVM) array configured for bit-addressable writes, the method comprising:
determining an amount of change in data to be updated within the NVM array;
determining, based on the amount of change in the data to be updated, whether to update the data by performing an in-place write without pre-set or by performing an in-place write with pre-set;
updating the data, in response to a determination to perform the in-place write without pre-set, by selectively performing individual bit-addressable writes within the data to update only particular bits of the data that need updating; and
updating the data, in response to a determination to perform the in-place write with pre-set, by pre-setting a portion of the NVM array to a first memory state and then updating only particular bits within the pre-set portion to a second memory state to encode the updated data.
13. The method of claim 12 , further comprising
performing the in-place write without pre-set by using bit-addressable writes to change selected bits from the first memory state to the second memory state and/or to change other selected bits from the second memory state to the first memory state; and
performing the in-place write with pre-set by initializing all bit states of the portion of the NVM array to the first memory state, then changing selected bits within the portion of the NVM array to the second memory state using bit-addressable writes to encode the updated data into the portion of the NVM array, without changing any bits within the portion of the NVM array from the second memory state to the first memory state.
14. The method of claim 12 , further comprising performing the bit-addressable writes by applying a set pulse to a bit to change the bit from the second memory state to the first memory state or by applying a re-set pulse to change the bit from the first state to the second state, where the set pulse takes longer than the re-set pulse to change the state of an individual bit.
15. The method of claim 14 , further comprising:
initializing all of the bit states of the portion of the NVM array to the first state by applying the set pulse to each bit within the portion of the NVM array; and
changing the selected bits from the first state to the second state to encode updated data in the NVM array by applying the re-set pulse to the selected bits.
16. The method claim 12 , further comprising comparing the amount of change in the data to be updated against a threshold, and performing the in-place write without pre-set if the amount is below the threshold, and performing the in-place write with pre-set if the amount is at or above the threshold.
17. The method of claim 12 , further comprising determining the amount of change in the data to be updated by one or more of predicting or estimating the amount of change in the data to be updated.
18. The method of claim 12 , wherein the data to be updated is generated from a multidimensional computation procedure and the method further comprises determining the amount of change in the data to be updated based on a current state of the multidimensional computation procedure.
19. The method of claim 18 , wherein the multidimensional computation procedure is a neural network computation procedure and wherein determining the amount is based on a factor derived from a current learning rate of the neural network computation procedure.
20. The method of claim 19 , further comprising repeating the determination at least once every iteration of the neural network computation procedure.
21. The method of claim 12 , further comprising regularizing the data by selectively disabling the updating of the data.
22. The method of claim 12 , further comprising regularizing the data by applying updates to only a portion of the data to be updated.