High current capable access device for three-dimensional solid-state memory
View Patent ↗The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.
1. A three-dimensional solid state array of memory cells, comprising:
a three-terminal device;
a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis;
a second electrical connector coupled to the three-terminal device;
a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and
a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and along a third axis perpendicular to both the second axis and the first axis.
2. The three dimensional solid state array of memory cells of claim 1 , where the three-terminal device is capable of conducting current in two directions to program the memory cell.
3. The three-dimensional solid state array of memory cells of claim 1 , wherein the three-terminal device is a surrounding gate electrode MESFET.
4. The three-dimensional solid state array of memory cells of claim 3 , wherein the MESFET comprises a channel and wherein the channel comprises polysilicon.
5. The three-dimensional solid state array of memory cells of claim 4 , wherein the polysilicon is doped.
6. The three-dimensional solid state array of memory cells of claim 5 , wherein the gate electrode comprises a noble metal.
7. The three-dimensional solid state array of memory cells of claim 6 , wherein the channel comprises a first end and a second end, wherein the first end is coupled to the first electrical connection and functions as a source electrode and wherein the second end is coupled to the second electrical connection and functions as a drain electrode.
8. The three-dimensional solid state array of memory cells of claim 1 , wherein the three-terminal device comprises a channel that has a first end and a second end, wherein the first end is coupled to the first electrical connection and functions as a source electrode and wherein the second end is coupled to the second electrical connection and functions as a drain electrode.
9. The three-dimensional solid state array of memory cells of claim 8 , wherein the three-terminal device is a MESFET, wherein the channel comprises polysilicon and wherein the MESFET comprises a gate electrode that comprises a noble metal.
10. A method of addressing a memory cell in a three-dimensional solid state array of memory cells, the memory cell comprising: a three-terminal device; a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the three-terminal device; a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis, the method comprising:
applying an electrical voltage or current to the first electrical connector;
applying an electrical voltage or current to the third electrical connector; and
applying an electrical voltage or current to the three-terminal device.
11. The method of claim 10 , wherein applying an electrical current to the three-terminal device comprises applying a current to a gate electrode of the three-terminal device to permit the electrical current applied to the first electrical connector to flow through a channel of the three-terminal device to the second electrical connector and to the memory cell.
12. The method of claim 11 , where the three-terminal device is capable of conducting current in two directions to program the memory cell.
13. The method of claim 12 , wherein the three-terminal device is a surrounding gate electrode MESFET.
14. The method of claim 13 , wherein the MESFET comprises a channel and wherein the channel comprises polysilicon.
15. The method of claim 14 , wherein the polysilicon is doped.
16. The method of claim 15 , wherein the gate electrode comprises a noble metal.
17. A method of addressing a memory cell in a three-dimensional solid state array of memory cells, the memory cell comprising a plurality of macro cells that each comprise a three-terminal device; a first electrical connector coupled to the three-terminal device, the first electrical connector extending along a first axis and a second axis perpendicular to the first axis; a second electrical connector coupled to the three-terminal device; a memory cell coupled to second electrical connector, the memory cell disposed along the second axis; and a third electrical connector coupled to the memory cell, the third electrical connector extending along the second axis and a third axis perpendicular to both the second axis and the first axis, the method comprising:
applying a first electrical voltage or current to the first electrical connectors of a first plurality of macro cells;
applying a second electrical voltage or current to the third electrical connectors of a second plurality of macro cells; and
applying a third electrical voltage or current to the three-terminal device of a third plurality of macro cells, wherein the first electrical current, the second electrical current and the third electrical current are collectively applied to a single macro cell.
18. The method of claim 17 , wherein the first plurality of macro cells are arranged in a first plane.
19. The method of claim 18 , wherein the second plurality of macro cells are arranged in a second plane that is perpendicular to the first plane.
20. The method of claim 19 , wherein the third plurality of macro cells are arranged in a third plane that is perpendicular to both the first plane and the second plane.
21. The method of claim 20 , wherein applying a third electrical current comprises applying the third electrical current to a gate electrode of each of the three-terminal devices of the third plurality of macro cells to permit the electrical current applied to the first electrical connector to flow through a channel of the three terminal device to the second electrical connector and to the memory cell.
22. The method of claim 21 , wherein the three-terminal device is a MESFET, wherein the MESFET is a surrounding gate electrode MESFET that comprises a channel, and wherein the channel comprises doped polysilicon, and wherein the gate electrode comprises a noble metal.