Three-dimensional memory device containing dummy via cavities and method for making same
A semiconductor structure includes a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers, a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers that overlies the first-tier alternating stack, a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel, a first contact via structure contacting one of the first-tier electrically conductive layers, a first-tier tubular dielectric spacer including a first inner sidewall contacting the first contact via structure and contacting each first-tier electrically conductive layer that overlies said one of the first-tier electrically conductive layers, and a first-tier pillar structure vertically extending through each first-tier electrically conductive layer and having a top surface that is coplanar with a topmost surface of the first-tier alternating stack.
1 . A semiconductor structure, comprising:
a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers;
a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers that overlies the first-tier alternating stack;
a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack;
a memory opening fill structure located in the memory opening and comprising a memory film and a vertical semiconductor channel;
a first contact via structure contacting one of the first-tier electrically conductive layers;
a first-tier tubular dielectric spacer comprising a first inner sidewall contacting a first cylindrical surface segment of the first contact via structure and comprising a first outer sidewall contacting each first-tier electrically conductive layer that overlies said one of the first-tier electrically conductive layers;
a second-tier tubular dielectric spacer comprising a second inner sidewall contacting a second cylindrical surface segment of the first contact via structure and comprising a second outer sidewall contacting each of the second-tier electrically conductive layers;
a first-tier pillar structure vertically extending through each first-tier electrically conductive layer in the first-tier alternating stack and having a top surface that is coplanar with a topmost surface of the first-tier alternating stack; and
an additional first-tier tubular dielectric spacer that laterally surrounds the first-tier pillar structure and having a same material composition and a same lateral thickness as the first-tier tubular dielectric spacer.
2 . The semiconductor structure of claim 1 , further comprising a peripheral circuit, wherein the first contact via structure is electrically connected to the peripheral circuit, and the first-tier pillar structure comprises a dummy pillar which is not electrically connected to the peripheral circuit.
3 . The semiconductor structure of claim 1 , further comprising a contact-level dielectric layer that overlies the second-tier alternating stack, wherein:
a top surface of the first contact via structure is located within a horizontal plane including a top surface of the contact-level dielectric layer; and
a portion of the first contact via structure that is embedded in the contact-level dielectric layer is in direct contact with the contact-level dielectric layer.
4 . The semiconductor structure of claim 1 , wherein:
an annular top surface of the first-tier tubular dielectric spacer is located within a horizontal plane including the topmost surface of the first-tier alternating stack; and
an annular top surface of the second-tier tubular dielectric spacer is located within a horizontal plane including a topmost surface of the second-tier alternating stack.
5 . The semiconductor structure of claim 4 , wherein an annular bottom surface of the second-tier tubular dielectric spacer is in contact with the annular top surface of the first-tier tubular dielectric spacer.
6 . The semiconductor structure of claim 1 , further comprising:
a second contact via structure contacting one of the second-tier electrically conductive layers; and
an additional second-tier tubular dielectric spacer laterally surrounding and contacting the second contact via structure and contacting each second-tier electrically conductive layer that overlies said one of the second-tier electrically conductive layers.
7 . The semiconductor structure of claim 6 , wherein the first-tier pillar structure underlies, is vertically spaced from and has an areal overlap in a plan view with the second contact via structure.
8 . The semiconductor structure of claim 1 , further comprising:
a third-tier alternating stack of third-tier insulating layers and third-tier electrically conductive layers that overlies the second-tier alternating stack, wherein the memory opening fill structure and the first contact via structure vertically extends through the third-tier alternating stack; and
a third-tier tubular dielectric spacer comprising a third inner sidewall contacting a third cylindrical surface segment of the first contact via structure and comprising a third outer sidewall contacting each of the third-tier electrically conductive layers.
9 . The semiconductor structure of claim 8 , further comprising:
a second-tier pillar structure vertically extending through the second-tier alternating stack and having a top surface that is coplanar with a topmost surface of the second-tier alternating stack and having a bottom surface that contacts the top surface of the first-tier pillar structure; and
an additional second-tier tubular dielectric spacer that laterally surrounds the second-tier pillar structure and having a same material composition and a same lateral thickness as the second-tier tubular dielectric spacer.
10 . The semiconductor structure of claim 9 , wherein an annular bottom surface of the additional second-tier tubular dielectric spacer is in contact with an annular top surface of the additional first-tier tubular dielectric spacer.
11 . The semiconductor structure of claim 1 , wherein the memory opening fill structure has a stepped vertical cross-sectional profile including a first tapered surface that extends through the first-tier alternating stack, a second tapered surface that extends through the second-tier alternating stack, and a first horizontal connecting surface that connects the first tapered surface and the second tapered surface and located within a horizontal plane including the top surface of the first-tier pillar structure.
12 . The semiconductor structure of claim 1 , wherein the first-tier pillar structure comprises a material that is selected from a semiconductor material, a carbon-based material including carbon atoms at an atomic percentage greater than 80%, or a polymer material.
13 . The semiconductor structure of claim 1 , wherein:
the first-tier pillar structure comprises a bottom surface that contacts a top surface of a bottommost first-tier insulating layer within the first-tier alternating stack, and comprises a top surface that contacts a bottom surface of a bottommost second-tier insulating layer within the second-tier alternating stack; and
the first-tier tubular dielectric spacer comprises an annular bottom surface that contacts a top surface of a bottommost first-tier insulating layer within the first-tier alternating stack, and comprises an annular top surface that contacts a bottom surface of a bottommost second-tier insulating layer within the second-tier alternating stack.
14 . The semiconductor structure of claim 1 , further comprising support pillar structures which extend through the first and the second alternating stacks, wherein the support pillar structures have a different material composition than the first-tier pillar structure.