Three-dimensional memory device including stairless word line contact structures for and method of making the same
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings located in a memory array region and vertically extending through the alternating stack;
memory opening fill structures located in the memory openings;
support pillar structures located in a contact region, vertically extending through the alternating stack, and comprising a dielectric material; and
laterally-isolated contact via assemblies located in the contact region, wherein each of the laterally-isolated contact via assemblies comprises a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a tubular dielectric spacer laterally surrounding the contact via structure,
wherein the support pillar structures comprise:
first support pillar structures that vertically extend through each layer within the alternating stack; and
second support pillar structures that are shorter than the first support pillar structures and contacting a respective one of the laterally-isolated contact via assemblies.
2. The three-dimensional memory device of claim 1 , wherein the alternating stack is free of stepped surfaces within the contact region.
3. The three-dimensional memory device of claim 1 , wherein a subset of the second support pillar structures contacts a horizontal bottom surface of a respective one of the contact via structures.
4. The three-dimensional memory device of claim 3 , wherein one of the contact via structures contacts horizontal top surfaces of at least two of the second support pillar structures.
5. The three-dimensional memory device of claim 3 , wherein one of the contact via structures contacts an entirety of a horizontal top surface of at least one of the second support pillar structures.
6. The three-dimensional memory device of claim 1 , wherein one of the laterally-isolated contact via assemblies contacts at least two of the second support pillar structures, and does not contact, and is laterally surrounded by, a subset of the first support pillar structures.
7. The three-dimensional memory device of claim 1 , wherein:
outer sidewalls of the tubular dielectric spacers have a taper angle; and
a subset of the second support pillar structures contacts a tapered outer sidewall of a respective one of the tubular dielectric spacers.
8. The three-dimensional memory device of claim 1 , wherein top surfaces of the contact via structures and the tubular dielectric spacers are located within a same horizontal plane.
9. The three-dimensional memory device of claim 1 , further comprising backside blocking dielectric layers located between each vertically neighboring pair of an insulating layer and an electrically conductive layer within the alternating stack, wherein each contact via structure contacts, and extends through, a respective one of the backside blocking dielectric layers.
10. The three-dimensional memory device of claim 9 , wherein each tubular dielectric spacer comprises an annular bottom surface that contacts a top surface of a respective one of the blocking dielectric layers.
11. The three-dimensional memory device of claim 10 , wherein each tubular dielectric spacer that vertically extends through a topmost one of the electrically conductive layers contacts a respective cylindrical sidewall of one of the backside blocking dielectric layers that contacts the topmost one of the electrically conductive layers.
12. The three-dimensional memory device of claim 1 , wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film.
13. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming memory openings through the alternating stack in a memory array region;
forming memory opening fill structures in the memory openings;
forming support pillar structures through the alternating stack in a contact region, wherein the support pillar structures comprise first support pillar structures and second support pillar structures;
forming via cavities in the contact region by performing anisotropic etch processes, wherein the first support pillar structures of the support pillar structures are not etched by the anisotropic etch processes, and top portions of the second support pillar structures of the support pillar structures are etched by the anisotropic etch processes;
forming sacrificial via fill structures in the via cavities;
replacing the sacrificial material layers with electrically conductive layers;
forming voids in volumes of the via cavities by removing the sacrificial via fill structures;
forming tubular dielectric spacers on sidewalls of the via cavities; and
forming contact via structures in remaining volumes of the via cavities on an inner sidewall of a respective one of the tubular dielectric spacers and directly on a top surface of a respective one of the electrically conductive layers.
14. The method of claim 13 , wherein each of the sacrificial material layers comprises a respective portion of a top surface that is physically exposed to a respective one of the via cavities upon formation of the via cavities.
15. The method of claim 14 , wherein forming the via cavities comprises sequentially performing N sets of via formation processing steps, wherein each i-th set of via formation processing steps comprises:
an i-th etch mask patterning step in which an i-th etch mask layer is formed over the alternating stack and is lithographically patterned to form openings therethrough;
an i-th anisotropic etch step in which at least one pair of an insulating layer and a sacrificial material layer is etched underneath the openings in the i-th etch mask layer; and
an i-th etch mask removal step in which the i-th etch mask layer is removed,
wherein N is an integer greater than 1, and i is any integer between 0 and N+1.
16. The method of claim 15 , wherein openings in a j-th etch mask layer includes a respective first subset of openings having an areal overlap with opening in a k-th etch mask layer and a respective second subset of openings that does not have any areal overlap with the openings in the k-th etch mask layer for any pair of j and k that are different from each other and selected from integers in a range between 0 and N+1.
17. The method of claim 15 , wherein:
an anisotropic etch step within the N sets of via formation processing steps etches a single pair of an insulating layer and a sacrificial material layer underneath each opening in a respective etch mask layer;
another anisotropic etch step within the N sets of via formation processing steps etches two pairs of an insulating layer and a sacrificial material layer underneath each opening in a respective etch mask layer; and
yet another anisotropic etch step within the N sets of via formation processing steps etches four pairs of an insulating layer and a sacrificial material layer underneath each opening in a respective etch mask layer.
18. The method of claim 13 , wherein a horizontal top surface of one of the second support pillar structures is physically exposed at a bottom surface of one of the via cavities.
19. The method of claim 13 , wherein a tapered sidewall surface of one of the second support pillar structures is physically exposed on a sidewall of one of the via cavities.
20. The method of claim 13 , further comprising:
forming backside recesses by removing the sacrificial material layers in the alternating stack;
depositing a backside blocking dielectric layer in backside recesses and on bottom surfaces of the sacrificial via fill structures, wherein the electrically conductive layers are formed in remaining volumes of the backside recesses after depositing the backside blocking dielectric layer; and
removing portions of the backside blocking dielectric layers after removing the sacrificial via fill structures, wherein each of the contact via structures is formed through an opening in a horizontally-extending portion of a respective one of the backside blocking dielectric layers.