Three-dimensional memory device containing multi-level word line contact wells and methods for manufacturing the same
A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.
1 . A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory openings vertically extending through the alternating stack;
memory opening fill structures located in the memory openings and comprising a respective memory film and a respective vertical semiconductor channel;
contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers;
dielectric fill structures located in the contact wells; and
an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers comprising a plurality of electrically conductive layers that are vertically spaced apart,
wherein a first one of the dielectric fill structures located in a first one of the contact wells comprises:
at least one dielectric liner located at a peripheral region of the first one of the contact wells; and
a dielectric fill material portion that is laterally surrounded by the at least one dielectric liner, wherein each contact via structure within the array of contact via structures is laterally offset inward from the plurality of primary sidewalls of the first one of the contact wells by a respective lateral offset distance that is greater than a total thickness of the at least one dielectric liner; and
wherein the at least one dielectric liner comprises:
a first dielectric liner that is in direct contact with the plurality of primary sidewalls of the first one of the contact wells and a plurality of bottom surface segments of the first one of the contact wells; and
a second dielectric liner having a vertically-extending portion in direct contact with an inner sidewall of the first dielectric liner and a horizontally-extending portion in direct contact top surface of a horizontally-extending portion of the first dielectric liner.
2 . The memory device of claim 1 , wherein:
each of the contact wells comprises a plurality of primary sidewalls each having a respective stepped bottom edge containing at least two horizontally-extending edge segments and at least one vertically-extending edge segment; and
each of the primary sidewalls comprises a respective top edge located entirely within a horizontal plane, and the top edges of the primary sidewalls are adjoined to each other to define a top periphery of each of the contact wells.
3 . The memory device of claim 2 , wherein:
each of the contact wells comprises a plurality of bottom surface segments that are vertically spaced apart from each other; and
each horizontally-extending edge segment of the stepped bottom edges of each of the contact wells coincides with an edge of a respective bottom surface segment of the plurality of bottom surface segments.
4 . The memory device of claim 2 , wherein each of the contact wells comprises a plurality of secondary sidewalls that are not vertically coincident with any of the plurality of primary sidewalls.
5 . The memory device of claim 2 , wherein:
the top periphery of each of the contact wells is located entirely within a first horizontal plane including a top surface of a topmost layer within the alternating stack;
a top surface of each of the dielectric fill structures is located entirely within the first horizontal plane; and
top surfaces of the array of contact via structures are located within a second horizontal plane overlying the first horizontal plane.
6 . The memory device of claim 1 , wherein:
each of the insulating layers has a first thickness;
each vertically neighboring pair of the insulating layers is vertically spaced from each other by a second thickness;
each contact via structure within the array of contact via structures vertically extends through a respective horizontally-extending portion of the at least one dielectric liner; and
the horizontally-extending portions of the at least one dielectric liner are vertically offset from each other by integer multiples of a sum of the first thickness and the second thickness.
7 . The memory device of claim 1 , wherein:
the first dielectric liner comprises a silicon oxide material, and the second dielectric liner comprises a dielectric material other than silicon oxide that laterally surrounds the dielectric fill material portion; and
the dielectric fill material portion comprises silicon oxide.
8 . The memory device of claim 1 , wherein:
each of the insulating layers and the electrically conductive layers within the alternating stack comprises lengthwise sidewalls that laterally extend along a first horizontal direction; and
the alternating stack comprises a memory block.
9 . The memory device of claim 8 , wherein:
the array of contact via structures comprises N rows of contact via structures arranged along the first horizontal direction;
each row of contact via structures within the N rows of contact via structures comprises a respective set of M contact via structures;
M is a first integer greater than 1; and
N is a second integer greater than 1.
10 . The memory device of claim 8 , wherein the array of contact via structures comprises an M×N rectangular array of contact via structures.
11 . The memory device of claim 1 , wherein:
a first one of the dielectric fill structures is in direct contact with each of the insulating layers within the alternating stack that overlies a horizontal plane including a bottommost surface of the first one of the dielectric fill structures; and
each of the electrically conductive layers within the alternating stack that overlies the horizontal plane is laterally spaced from the first one of the dielectric fill structures by a vertically-extending portion of a respective backside blocking dielectric layer.
12 . The memory device of claim 1 , wherein a first one of the dielectric fill structure is in direct contact with each of the insulating layers and each of the electrically conductive layers within the alternating stack that overlie a horizontal plane including a bottommost surface of the first one of the dielectric fill structures.
13 . The memory device of claim 1 , wherein the contact wells are separated by different distances from each other.
14 . The memory device of claim 1 , wherein the first dielectric liner comprises:
a first horizontally-extending dielectric liner portion overlying a first bottom surface segment of the first one of the contact wells;
a second horizontally-extending dielectric liner portion overlying a second bottom surface segment of the first one of the contact wells; and
a vertically-extending connecting dielectric liner portion that connects the first horizontally-extending dielectric liner portion and the second horizontally-extending dielectric liner portion.
15 . The memory device of claim 1 , wherein the second dielectric liner is in direct contact with the dielectric fill material portion.
16 . The memory device of claim 15 , wherein the first dielectric liner is not in direct contact with the dielectric fill material portion.
17 . The memory device of claim 1 , wherein a first contact via structure within the array of contact via structures is in direct contact with the dielectric material portion, the second dielectric liner, and the first dielectric liner.
18 . The memory device of claim 1 , wherein top surfaces of the array of contact via structures are located above a horizontal plane including a topmost surface of the dielectric material portion.
19 . The memory device of claim 18 , wherein:
a topmost surface of the first dielectric liner and a topmost surface of the second dielectric liner are located within a horizontal plane including the topmost surface of the dielectric material portion;
a bottommost surface of the first dielectric liner is located above a horizontal plane including a bottommost surface of the alternating stack; and
the dielectric material portion is located above, and is vertically spaced from, horizontally-extending portions of the first dielectric liner.
20 . The memory device of claim 18 , further comprising drain contact via structures contacting the memory opening fill structures, wherein top surfaces of the drain contact via structures and the top surfaces of the array of contact via structures are located in a same horizontal plane.