Low-resistance top contact on VTFET

1. A method of forming a semiconductor device, the method comprising:

forming a vertical semiconductor fin including a bottom end that contacts a semiconductor substrate;

forming a top source/drain region on a top end of the vertical semiconductor fin and on sidewalls of the vertical semiconductor fin, the top source/drain region separated from the semiconductor substrate by the vertical semiconductor fin;

forming an electrically conductive cap on an outer surface of the top source/drain region;

forming a first dielectric trench liner adjacent a first side of the electrically conductive cap and forming a second dielectric liner adjacent a second side of the electrically conductive cap opposite the first side; and

forming an electrically conductive contact via between the first and second dielectric liners and in ohmic connection with the electrically conductive cap.

2. The method of claim 1 , wherein forming the electrically conductive cap comprises:

depositing an electrically conductive film on the outer surface of the top source/drain region; and

performing a temperature anneal process to form the electrically conductive cap by converting a portion of the electrically conductive film into a binary compound of a semiconductor material included in the top source/drain region.

3. The method of claim 2 , wherein the electrically conductive film is converted to a silicide material that defines the conductive cap.

4. The method of claim 2 , wherein forming the first and second dielectric liners comprises:

after performing the anneal process, recessing a remaining non-converted portion of the electrically conductive film to form a first vertical cavity adjacent the first side of the electrically conductive cap and forming a second vertical cavity adjacent the second side of the electrically conductive cap; and

filling the first and second vertical cavities with a dielectric material to form the first and second dielectric trench liners.

5. The method of claim 4 , wherein forming the top source/drain region comprises epitaxially growing silicon from the top end of the vertical semiconductor fin.

6. The method of claim 5 , wherein forming the electrically conductive contact via comprises:

encapsulating the electrically conductive cap with a dielectric material;

selectively forming a trench that extends through the dielectric material and stops on the electrically conductive cap; and

depositing an electrically conductive material in the trench to establish ohmic connection with the electrically conductive cap.

7. The method of claim 6 , further comprising forming a gate structure that wraps completely around all sidewalls the vertical semiconductor fin, the gate structure including a bottom portion that directly contacts the semiconductor substrate and a top portion that directly contacts the top source/drain region.

8. The method of claim 7 , wherein gate structure is interposed between the semiconductor substrate and the electrically conductive cap.