Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers containing a terrace region comprising a plurality of steps;

memory stack structures extending through the alternating stack;

a retro-stepped dielectric material portion overlying the terrace region;

first laterally isolated contact structures each including a respective first contact via structure and a respective first dielectric spacer, wherein the respective first contact via structure contacts a top surface of a respective first electrically conductive layer of the electrically conductive layers in a respective step of the plurality of steps; and

second laterally isolated contact structures including a respective second contact via structure and a respective second dielectric spacer, wherein the respective second contact via structure extends through the respective first electrically conductive layer in the respective step and contacts a top surface of a respective second electrically conductive layer of the electrically conductive layers which underlies the first electrically conductive layer in the respective step.

2. The three-dimensional memory device of claim 1 , wherein:

the plurality of steps in the terrace region comprise stepped surfaces that include a plurality of vertical surfaces that are laterally spaced apart along a first horizontal direction and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction;

the respective second dielectric spacer vertically extends through the retro-stepped dielectric material portion and contacts an annular top surface segment of the respective second electrically conductive layer and a cylindrical sidewall surface of the respective first electrically conductive layer; and

the respective first dielectric spacer vertically extends through the retro-stepped dielectric material portion and contacts only the single first electrically conductive layer of the electrically conductive layers.

3. The three-dimensional memory device of claim 2 , wherein:

the respective first contact via structure contacts a top surface segment of the respective single first electrically conductive layer; and

the respective second contact via structure contacts a top surface segment of the respective second electrically conductive layer.

4. The three-dimensional memory device of claim 2 , wherein the stepped surfaces further comprise a plurality of horizontal surfaces that are laterally spaced apart along the first horizontal direction, laterally extend along the second horizontal direction, and are interlaced with the plurality of vertical surfaces.

5. The three-dimensional memory device of claim 4 , wherein for a first horizontal surface selected from the plurality of horizontal surfaces:

one of the first laterally-isolated contact structures vertically extends to or through the first horizontal surface; and

one of the second laterally-isolated contact structures vertically extends through the first horizontal surface.

6. The three-dimensional memory device of claim 5 , wherein the one of the second laterally-isolated contact structures is laterally offset from the one of the first laterally-isolated contact via structures along the second horizontal direction.

7. The three-dimensional memory device of claim 1 , wherein:

the first laterally-isolated contact structures are arranged along the first horizontal direction in a first row;

the second laterally-isolated contact structures are arranged along the first horizontal direction in a second row; and

the second row is laterally offset from the first row along the second horizontal direction.

8. The three-dimensional memory device of claim 1 , wherein the first contact via structures and the second contact via structures have top surfaces located within a horizontal plane located at or above a topmost surface of the alternating stack.

9. The three-dimensional memory device of claim 8 , wherein the first dielectric spacers and the second dielectric spacers have a same dielectric material composition, have a same lateral distance between a respective inner sidewall and a respective outer sidewall, and have top surfaces within the horizontal plane including the top surfaces of the first contact via structures and the second contact via structures.

10. The three-dimensional memory device of claim 1 , wherein the first contact via structures and the second contact via structures have a same or a different material composition than the electrically conductive layers.

11. The three-dimensional memory device of claim 2 , further comprising:

a first backside trench fill structure laterally extending along the first horizontal direction and contacting first sidewalls of each layer within the alternating stack; and

a second backside trench fill structure laterally extending along the first horizontal direction and contacting second sidewalls of each layer within the alternating stack,

wherein each vertical surface within the plurality of vertical surfaces of the stepped surfaces laterally extends straight along the second horizontal direction between the first backside trench fill structure and the second backside trench fill structure.

12. The three-dimensional memory device of claim 11 , wherein:

the stepped surfaces continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack;

the stepped surfaces further comprise a plurality of horizontal surfaces that are interlaced with and adjoined to the plurality of vertical surfaces; and

each horizontal surface within the plurality of horizontal surfaces of the stepped surfaces has a respective uniform width along the first horizontal direction and laterally extends along the second horizontal direction between the first backside trench fill structure and the second backside trench fill structure.

13. The three-dimensional memory device of claim 2 , wherein:

the retro-stepped dielectric material portion comprises a contiguous set of surfaces that includes horizontal bottom surface segments and vertical surface segments;

the horizontal bottom surface segments are vertically spaced apart from each other and are laterally spaced apart from each other; and

each of the horizontal bottom surface segments other than a bottommost one of the horizontal bottom surface segments is adjoined to a respective pair of vertical surfaces segments of the vertical surface segments of the retro-stepped dielectric material portion.

14. The three-dimensional memory device of claim 2 , further comprising third laterally-isolated contact structures, each including a respective third contact via structure and a respective third dielectric spacer, wherein the respective third contact via structure extends through the first and the second electrically conductive layers in the respective step and contacts a top surface of a third electrically conductive layer of the electrically conductive layers in the respective step.

15. A method of forming a three-dimensional memory device, comprising:

forming a combination of an alternating stack of insulating layers and electrically conductive layers, memory stack structures, and a retro-stepped dielectric material portion over a substrate, wherein the memory stack structures vertically extend through the alternating stack, the alternating stack comprises stepped surfaces that continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack, and the retro-stepped dielectric material portion overlies the stepped surfaces of the alternating stack;

forming first via cavities and second via cavities through the retro-stepped dielectric material portion, wherein each of the first via cavities and the second via cavities vertically extends through the retro-stepped dielectric material portion and has a bottom surface that coincides with a top surface segment of a respective one of the electrically conductive layers;

vertically extending the second via cavities through a respective pair of an electrically conductive layer and an insulating layer while masking the first via cavities, whereby a top surface of a respective underlying electrically conductive layer is physically exposed underneath each of the second via cavities; and

forming first laterally-isolated contact structures in the first via cavities and second laterally-isolated contact structures in the second via cavities, wherein each of the first laterally-isolated contact structures includes a respective first contact via structure and a respective first dielectric spacer, and each of the second contact via structures comprises a respective second contact via structure and a respective second dielectric spacer.

16. The method of claim 15 wherein:

the respective first dielectric spacer vertically extends through the retro-stepped dielectric material portion and contacts no more than a respective single first electrically conductive layer of the electrically conductive layers of the alternating stack; and

the respective second dielectric spacer vertically extends through the retro-stepped dielectric material portion and contacts an annular top surface segment of a respective second electrically conductive layer of the electrically conductive layers of the alternating stack and a cylindrical sidewall surface of the respective first electrically conductive layer that overlies the respective second electrically conductive layer.

17. The method of claim 15 , wherein:

the first via cavities are arranged along a first horizontal direction in a first row;

the second via cavities are arranged along the first horizontal direction in a second row; and

the second row is laterally offset from the first row along the second horizontal direction.

18. The method of claim 17 , further comprising:

forming a hard mask layer over the alternating stack and the retro-stepped dielectric material portion;

forming an array of openings in the hard mask layer; and

performing an anisotropic etch process that etches a material of the retro-stepped dielectric material portion selective to a material of the electrically conductive layers employing the hard mask layer as an etch mask to form the first via cavities and the second via cavities through the retro-stepped dielectric material portion.

19. The method of claim 18 , further comprising:

forming a patterned etch mask layer over the hard mask layer after formation of the first via cavities and the second via cavities, wherein the patterned etch mask layer fills the first via cavities; and

performing an anisotropic etch process that etches the respective pair of the electrically conductive layer and the insulating layer underneath each second via cavity while the patterned etch mask layer fills the first via cavities.

20. The method of claim 18 , further comprising:

forming a patterned etch mask layer over the hard mask layer after formation of the first via cavities and the second via cavities, wherein the patterned etch mask layer covers the first via cavities; and

performing an anisotropic etch process that etches the respective pair of the electrically conductive layer and the insulating layer underneath each second via cavity while the patterned etch mask layer covers the first via cavities.