Vertical resistor in 3D memory device with two-tier stack
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
1. A semiconductor device, comprising:
a substrate;
a stack in a memory cell area of the substrate, the stack comprising a first tier and a second tier on the first tier, the first tier comprising a first set of alternating control gate layers and dielectric layers and the second tier comprising a second set of alternating control gate layers and dielectric layers, the stack comprising memory holes, each memory hole comprises a portion in the first tier and a portion in the second tier, and memory films extend along a wall of each memory hole;
a transistor formed on the substrate in a peripheral area, peripheral to the memory cell area, the transistor is in a circuit;
a first column in the peripheral area, the first column comprises polysilicon and extends from a terminal of the transistor to a height of a top of the first tier, wherein a doping concentration of the first column decreases progressively moving downward from a top of the first column; and
a second column which extends from the height of the top of the first tier to a height of a top of the second tier, the second column is electrically connected to the first column.
2. The semiconductor device of claim 1 , wherein:
the second column comprises a metal pillar; and
a top surface of the first column touches a bottom surface of the metal pillar.
3. The semiconductor device of claim 2 , wherein:
a top surface of the first column provides an ohmic contact to the metal pillar.
4. The semiconductor device of claim 1 , wherein:
the first column comprises ion implanted at different depths and different doping concentrations.
5. The semiconductor device of claim 1 , further comprising:
a resistor in the circuit, the resistor comprising the first column.
6. The semiconductor device of claim 1 , wherein:
the second column comprises metal; and
a top surface of the first column touches a bottom surface of the metal.
7. The semiconductor device of claim 1 , wherein:
the first column comprises at least three regions with different doping concentrations.
8. The semiconductor device of claim 1 , wherein:
a doping concentration of the top of the first column is about 1E19-22/cm3.
9. The semiconductor device of claim 1 , wherein:
at least a bottom portion of the second column comprises polysilicon; and
a resistor in the circuit comprises the polysilicon in the at least the bottom portion of the second column.
10. The semiconductor device of claim 1 , wherein:
the second column comprises polysilicon; and
a doping concentration of the polysilicon in the second column is different than a doping concentration of the polysilicon in the first column by at least an order of magnitude.
11. The semiconductor device of claim 1 , wherein:
a bottom of the first column is in contact with an n or p type diffusion region of the transistor in the substrate.
12. The semiconductor device of claim 1 , wherein:
a bottom of the first column is in contact with a control gate of the transistor.
13. The semiconductor device of claim 1 , wherein:
the first column is tapered, becoming narrower at a bottom of the first column;
the second column is tapered, becoming narrower at a bottom of the second column; and
a top of the first column is wider than a bottom of the second column.
14. The semiconductor device of claim 1 , wherein:
the first column extends through a silicon nitride layer to the terminal of the transistor.