Data storage device and method for dynamic prediction of random read with low memory consumption
A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
1. A data storage device comprising:
a volatile memory;
a non-volatile memory; and
a controller configured to:
allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory;
determine whether an accuracy of the predicted next read commands is below a threshold for increasing system performance; and
in response to determining that the accuracy of the predicted next read commands is below the threshold for increasing system performance, increase system performance by:
decreasing the amount of space in the volatile memory allocated for the history pattern matcher data structure; and
increasing an amount of space in the volatile memory allocated for a flash translation layer cache.
2. The data storage device of claim 1 , wherein the amount of space in the volatile memory allocated for the history pattern matcher data structure is based on queue depth.
3. The data storage device of claim 1 , wherein the amount of space in the volatile memory allocated for the history pattern matcher data structure is based on an amount of sequential data received from the host.
4. The data storage device of claim 1 , wherein the amount of space in the volatile memory allocated for the history pattern matcher data structure is based on data address fragmentation.
5. The data storage device of claim 1 , wherein the amount of space in the volatile memory allocated for the history pattern matcher data structure is based on data stream type.
6. The data storage device of claim 1 , wherein the amount of space in the volatile memory allocated for the history pattern matcher data structure is based on an amount of read and/or write commands processed by the data storage device.
7. The data storage device of claim 1 , wherein the controller is further configured to allocate the amount of space in the volatile memory for the history pattern matcher data structure using a machine-learning algorithm.
8. The data storage device of claim 1 , wherein the controller is further configured to determine an expected increase in accuracy based on different amounts of space allocated in the volatile memory.
9. The data storage device of claim 1 , wherein the controller is further configured to dynamically allocate a different amount of space in the volatile memory to improve cache performance.
10. The data storage device of claim 1 , wherein the controller is further configured to predict a future change in data patterns and dynamically allocate a different amount of space in the volatile memory before the future change in the data patterns occurs.
11. The data storage device of claim 1 , wherein the controller is further configured to use a classification system to determine what to store in the history pattern matcher data structure.
12. The data storage device of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.
13. A method comprising:
performing the following in a data storage device comprising a volatile memory and in communication with a host:
predicting next read commands received from the host;
determining whether a success rate of the predicted next read commands is less than a threshold for increasing system performance; and
in response to determining that the success rate is less than the threshold for increasing system performance, increasing system performance by:
decreasing an amount of space allocated in the volatile memory used for predicting next read commands; and
increasing an amount of space in the volatile memory allocated for a flash translation layer cache.
14. The method of claim 13 , wherein the success rate is determined using a machine-learning algorithm.
15. The method of claim 13 , further comprising determining success rates for a plurality of different allocation sizes.
16. The method of claim 13 , further comprising dynamically allocating a different amount of space in the volatile memory to improve cache performance.
17. The method of claim 13 , further comprising predicting a future change in data patterns and dynamically allocating a different amount of space in the volatile memory before the change in the data patterns occurs.
18. The method of claim 13 , wherein the amount of space allocated in the volatile memory is allocated for a history pattern matcher data structure.
19. The method of claim 18 , further comprising using a classification system to determine what to store in the history pattern matcher data structure.
20. A data storage device comprising:
a volatile memory;
a non-volatile memory;
controller means for:
allocating an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory;
determining whether an accuracy of the predicted next read commands is below a threshold for increasing system performance; and
in response to determining that the accuracy of the predicted next read commands is below the threshold for increasing system performance:
decreasing the amount of space in the volatile memory allocated for the history pattern matcher data structure; and
increasing an amount of space in the volatile memory allocated for a flash translation layer cache.