Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses
A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.
1 . A memory apparatus, comprising:
memory cells; and
a control means configured to:
adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming, and
program non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.
2 . The memory apparatus as set forth in claim 1 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, and the control means is further configured to:
determine a number of a plurality of program pulses applied to checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state; and
identify ones of the word lines connected to the checkpoint ones of the memory cells as susceptible to over-programming based on the number of the plurality of program pulses applied to the checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state.
3 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to adjust both the blind program pulses applied to the one of the word lines connected to the memory cells being programmed and one of the bit line voltages applied to one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
4 . The memory apparatus as set forth in claim 3 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states and the control means is further configured to adjust both the blind program pulses and one of the bit line voltages exclusively for the memory cells targeted for specific ones of the plurality of data states in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
5 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to adjust only the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
6 . The memory apparatus as set forth in claim 5 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming are grouped into a plurality of bit line voltage groups for the non-checkpoint states according to a quantity of the plurality of data states each of the non-checkpoint states is spaced from the checkpoint state associated therewith, and the control means is further configured to:
select one of the bit line voltages applied to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming based on which of the bit line voltage groups corresponds to the one of the non-checkpoint states targeted for the memory cells being programmed; and
apply the one of the bit line voltages selected to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
7 . The memory apparatus of claim 1 , wherein the control means is further configured to adjust only the verify low voltage for the checkpoint state in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
8 . A controller in communication with a memory apparatus including memory cells, the controller configured to:
instruct the memory apparatus to adjust at least one of blind program pulses applied to one of a word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming; and
instruct the memory apparatus to program non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.
9 . The controller as set forth in claim 8 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, and the controller is further configured to:
instruct the memory apparatus to determine a number of a plurality of program pulses applied to checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state; and
instruct the memory apparatus to identify ones of the word lines connected to the checkpoint ones of the memory cells as susceptible to over-programming based on the number of the plurality of program pulses applied to the checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state.
10 . The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to adjust both the blind program pulses applied to the one of the word lines connected to the memory cells being programmed and one of the bit line voltages applied to one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
11 . The controller as set forth in claim 10 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states and the controller is further configured to instruct the memory apparatus to adjust both the blind program pulses and one of the bit line voltages exclusively for the memory cells targeted for specific ones of the plurality of data states in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
12 . The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to adjust only the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
13 . The controller as set forth in claim 12 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming are grouped into a plurality of bit line voltage groups for the non-checkpoint states according to a quantity of the plurality of data states each of the non-checkpoint states is spaced from the checkpoint state associated therewith, and the controller is further configured to:
select one of the bit line voltages applied to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming based on which of the bit line voltage groups corresponds to the one of the non-checkpoint states targeted for the memory cells being programmed; and
instruct the memory apparatus to apply the one of the bit line voltages selected to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
14 . A method of operating a memory apparatus including memory cells, the method comprising the steps of:
adjusting at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming; and
programing non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.
15 . The method as set forth in claim 14 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, and the method further includes the steps of:
determining a number of a plurality of program pulses applied to checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state; and
identifying ones of the word lines connected to the checkpoint ones of the memory cells as susceptible to over-programming based on the number of the plurality of program pulses applied to the checkpoint ones of the memory cells targeted for the checkpoint state necessary for the checkpoint ones of the memory cells to have the threshold voltage above the verify low voltage for the checkpoint state.
16 . The method as set forth in claim 14 , further including the step of adjusting both the blind program pulses applied to the one of the word lines connected to the memory cells being programmed and one of the bit line voltages applied to one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
17 . The method as set forth in claim 16 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states and the method further includes the step of adjusting both the blind program pulses and one of the bit line voltages exclusively for the memory cells targeted for specific ones of the plurality of data states in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
18 . The method as set forth in claim 14 , further including the step of adjusting only the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
19 . The method as set forth in claim 18 , wherein the memory cells are configured to store a threshold voltage corresponding to one of a plurality of data states including the checkpoint state and non-checkpoint states associated with the checkpoint state, the bit line voltages applied to the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming are grouped into a plurality of bit line voltage groups for the non-checkpoint states according to a quantity of the plurality of data states each of the non-checkpoint states is spaced from the checkpoint state associated therewith, and the method further includes the steps of:
selecting one of the bit line voltages applied to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming based on which of the bit line voltage groups corresponds to the one of the non-checkpoint states targeted for the memory cells being programmed; and
applying the one of the bit line voltages selected to the one of the bit lines coupled to the memory cells being programmed in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.
20 . The method of claim 14 , further including the step of adjusting only the verify low voltage for the checkpoint state in response to determining the one of the word lines connected to the memory cells being programmed is susceptible to over-programming.