Soft information for punctured bit estimation in a data storage device
A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.
1. A memory controller, comprising:
a memory interface configured to receive a punctured codeword read from a non-volatile memory; and
a control circuit coupled to the memory interface and configured to:
determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword,
determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit,
determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit, and
decode the punctured codeword using the LLR value for the punctured bit.
2. The memory controller of claim 1 , wherein the control circuit is further configured to determine the error probability values for the plurality of check nodes based on a channel bit error rate and check degrees associated with the plurality of check nodes.
3. The memory controller of claim 2 , wherein all of the check degrees associated with the plurality of check nodes have the same value.
4. The memory controller of claim 1 , wherein, to determine the LLR value for the punctured bit based on the error probability value for the punctured bit, the control circuit is further configured to:
determine a reliability indicator based on the error probability value for the punctured bit, wherein the reliability indicator indicates whether an estimated value of the punctured bit is reliable or unreliable, and
determine the LLR value for the punctured bit based on the reliability indicator.
5. The memory controller of claim 4 , wherein, to determine the reliability indicator based on the error probability value for the punctured bit, the control circuit is further configured to:
compare the error probability value for the punctured bit to a threshold,
set the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the error probability value for the punctured bit is greater than the threshold, and
set the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the error probability value for the punctured bit is less than or equal to the threshold.
6. The memory controller of claim 4 , wherein, to determine the reliability indicator based on the error probability value for the punctured bit, the control circuit is further configured to:
determine a number of unsatisfied check nodes associated with the punctured bit,
determine a reliability metric as a difference between the number of unsatisfied check nodes associated with the punctured bit and half of the variable degree associated with the punctured bit,
determine a threshold based on the error probability value for the punctured bit,
compare the reliability metric to the threshold,
set the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the reliability metric is greater than the threshold, and
set the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the reliability metric is less than or equal to the threshold.
7. The memory controller of claim 4 , wherein the control circuit is further configured to:
set the LLR value for the punctured bit to 0 when the reliability indicator indicates that the estimated value of the punctured bit is unreliable, and
set the LLR value for the punctured bit to either a predetermined positive integer or a predetermined negative integer when the reliability indicator indicates that the estimated value of the punctured bit is reliable.
8. A method performed by a control circuit coupled to a non-volatile memory, comprising:
receiving a punctured codeword read from the non-volatile memory;
determining error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword;
determining an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit;
determining a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit; and
decoding the punctured codeword using the LLR value for the punctured bit.
9. The method of claim 8 , wherein determining the error probability values for the plurality of check nodes associated with the punctured bit includes determining the error probability values for the plurality of check nodes associated with the punctured bit based on a channel bit error rate and check degrees associated with the plurality of check nodes.
10. The method of claim 9 , wherein all of the check degrees associated with the plurality of check nodes have the same value.
11. The method of claim 8 , wherein determining the LLR value for the punctured bit based on the error probability value for the punctured bit further includes:
determining a reliability indicator based on the error probability value for the punctured bit, wherein the reliability indicator indicates whether an estimated value of the punctured bit is reliable or unreliable, and
determining the LLR value for the punctured bit based on the reliability indicator.
12. The method of claim 11 , wherein determining the reliability indicator based on the error probability value for the punctured bit further includes:
comparing the error probability value for the punctured bit to a threshold,
setting the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the error probability value for the punctured bit is greater than the threshold, and
setting the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the error probability value for the punctured bit is less than or equal to the threshold.
13. The method of claim 11 , wherein determining the reliability indicator based on the error probability value for the punctured bit further includes:
determining a number of unsatisfied check nodes associated with the punctured bit,
determining a reliability metric as a difference between the number of unsatisfied check nodes associated with the punctured bit and half of the variable degree associated with the punctured bit,
determining a threshold based on the error probability value for the punctured bit,
comparing the reliability metric to the threshold,
setting the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the reliability metric is greater than the threshold, and
setting the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the reliability metric is less than or equal to the threshold.
14. The method of claim 11 , further comprising:
setting the LLR value for the punctured bit to 0 when the reliability indicator indicates that the estimated value of the punctured bit is unreliable, and
setting the LLR value for the punctured bit to either a predetermined positive integer or a predetermined negative integer when the reliability indicator indicates that the estimated value of the punctured bit is reliable.
15. An apparatus, comprising:
means for receiving a punctured codeword read from a non-volatile memory;
means for determining error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword;
means for determining an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit;
means for determining a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit; and
means for decoding the punctured codeword using the LLR value for the punctured bit.
16. The apparatus of claim 15 , wherein the means for determining the error probability values for the plurality of check nodes associated with the punctured bit is further configured to determine the error probability values for the plurality of check nodes associated with the punctured bit based on a channel bit error rate and check degrees associated with the plurality of check nodes.
17. The apparatus of claim 16 , wherein all of the check degrees associated with the plurality of check nodes have the same value.
18. The apparatus of claim 15 , wherein the means for determining the LLR value for the punctured bit based on the error probability value for the punctured bit is further configured to:
determine a reliability indicator based on the error probability value for the punctured bit, wherein the reliability indicator indicates whether an estimated value of the punctured bit is reliable or unreliable, and
determine the LLR value for the punctured bit based on the reliability indicator.
19. The apparatus of claim 18 , wherein the means for determining the LLR value for the punctured bit based on the error probability value for the punctured bit is further configured to:
compare the error probability value for the punctured bit to a threshold,
set the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the error probability value for the punctured bit is greater than the threshold, and
set the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the error probability value for the punctured bit is less than or equal to the threshold.
20. The apparatus of claim 18 , wherein the means for determining the LLR value for the punctured bit based on the error probability value for the punctured bit is further configured to:
determining a number of unsatisfied check nodes associated with the punctured bit,
determine a reliability metric as a difference between the number of unsatisfied check nodes associated with the punctured bit and half of the variable degree associated with the punctured bit,
determine a threshold based on the error probability value for the punctured bit,
compare the reliability metric to the threshold,
set the reliability indicator to indicate that the estimated value of the punctured bit is reliable when the reliability metric is greater than the threshold, and
set the reliability indicator to indicate that the estimated value of the punctured bit is unreliable when the reliability metric is less than or equal to the threshold.