IP Library Granted Patent US 11,269,764
Granted Patent B2
US 11,269,764 · App. 15/911,815 · Granted Mar 8, 2022

Storage system and method for adaptive scheduling of background operations

Inventors: Judah Gamliel Hahn (Ofra, IL); Alexander Bazarsky (Holon, IL); Ariel Navon (Revava, IL); David Gur (Ofra, IL)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F3/064G06F3/0625G06F3/0659G06F3/0679G06F12/0253G06F15/76G06N20/00G06F2212/7205
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Quick Facts
Patent No.
US 11,269,764
App. No.
15/911,815
Granted
Mar 8, 2022
Kind
B2
Abstract

A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Claims (45)

1. A method for adaptive scheduling of a background operation, the method comprising:

performing in a storage system in communication with a host, wherein the storage system is configured to operate in a high-power mode and a low-power mode and comprises a memory, wherein the storage system uses more power in the high-power mode than in the low-power mode:

completing a host operation in the memory at an end host operation time, wherein the storage system is in the high-power mode when performing the host operation and remains in the high-power mode for a known period of time following the end host operation time, after which the storage system enters the low-power mode;

estimating a likelihood that another host operation will be requested by the host during the known period of time following the end host operation time, the estimating comprising:

for each stored pattern of a plurality of write patterns stored in a read only memory (ROM) of the storage system: comparing a current pattern of host operations to the stored pattern and generating a score indicating a matching level of the current pattern of host operations to the stored pattern, thereby generating a plurality of scores, each indicating a matching level of the current pattern of host operations to one of the plurality of write patterns stored in the ROM, wherein each of the plurality of write patterns comprises one or more logical block addresses (LBAs) or one or more LBA ranges that a user is expected to write,

comparing each of the plurality of scores against a threshold, and

selecting a matched stored pattern, from among the plurality of write patterns stored in the ROM, corresponding to a score which exceeds the threshold, and

predicting how long it will be before another host operation will be received based on the matched stored pattern;

determining whether there will be enough time to perform the background operation in the memory during the known period of time based on the estimation of the likelihood that another host operation will be requested by the host during the known period of time; and

based on the determining whether there will be enough time to perform the background operation in the memory during the known period of time, determining whether to perform the background operation in the memory.

2. The method of claim 1 , wherein estimating whether there will be enough time to perform the background operation comprises using machine learning.

3. The method of claim 1 , wherein the memory comprises a three- dimensional memory.

4. The method of claim 1 , wherein the storage system is embedded in the host.

5. The method of claim 1 , wherein the storage system is removably connected to the host.

6. A storage system comprising:

a memory; and

a controller configured to:

operate in a high-power and a low-power mode, wherein the storage system uses more power in the high-power mode than in the low-power mode;

remain in the high-power mode during a known period of time after a host operation is performed, after which the storage system enters the low-power mode;

estimate a likelihood that the host will request another host operation during the known period of time by:

for each stored pattern of a plurality of write patterns stored in a read only memory (ROM) of the storage system: comparing a current pattern of host operations to the stored pattern and generating a score indicating a matching level of the current pattern of host operations to the stored pattern, thereby generating a plurality of scores, each indicating a matching level of the current pattern of host operations to one of the plurality of write patterns stored in the ROM, wherein each of the plurality of write patterns comprises one or more logical block addresses (LBAs) or one or more LBA ranges that a user is expected to write,

comparing each of the plurality of scores against a threshold, and

selecting a matched stored pattern, from among the plurality of write patterns stored in the ROM, corresponding to a score which exceeds the threshold, and

predicting how long it will be before another host operation will be received based on the matched stored pattern;

determine whether there will be enough time to perform a background operation based on the estimation of the likelihood that the host will request another host operation during the known period of time; and

based on the determination of whether there will be enough time remaining in the known period of time, determine whether to perform the background operation.

7. The storage system of claim 6 , wherein the patterns are stored in the ROM when the storage system is off-line with respect to the host.

8. The storage system of claim 6 , wherein the controller is configured to use machine learning to perform the estimation of whether there will be enough time remaining in the known period of time to perform the background operation.

9. The storage system of claim 6 , wherein the memory comprises a three- dimensional memory.

10. The storage system of claim 6 , wherein the storage system is embedded in a host.

11. The storage system of claim 6 , wherein the storage system is removably connected to a host.

12. A storage system comprising:

a memory;

means for operating in a high-power mode and a low-power mode, wherein the storage system uses more power in the high-power mode than in the low-power mode;

means for remaining in the high-power mode during a known period of time after a host operation is performed, after which the storage system enters the low-power mode;

means for estimating a likelihood that another host operation will be received during the known period of time, the means for estimating comprising:

for each stored pattern of a plurality of write patterns stored in a read only memory (ROM) of the storage system: means for comparing a current pattern of host operations to the stored pattern and generating a score indicating a matching level of the current pattern of host operations to the stored pattern, thereby generating a plurality of scores, each indicating a matching level of the current pattern of host operations to one of the plurality of write patterns stored in the ROM, wherein each of the plurality of write patterns comprises one or more logical block addresses (LBAs) or one or more LBA ranges that a user is expected to write,

means for comparing each of the plurality of scores against a threshold, and

means for selecting a matched stored pattern, from among the plurality of write patterns stored in the ROM, corresponding to a score which exceeds the threshold, and

means for predicting how long it will be before another host operation will be received based on a matching result of a comparison of a current pattern of host operations to write patterns stored in the ROM;

means for determining whether there will be enough time to perform the background operation based on the estimation of the likelihood that the host will request another host operation during the known period of time; and

means for determining whether to perform the background operation based on the determination of whether there will be enough time during the known period of time.

13. The storage system of claim 12 , wherein the means for determining whether there will be enough time uses pattern matching.

14. The storage system of claim 12 , wherein the means for determining whether there will be enough time uses machine learning.

15. The storage system of claim 12 , wherein the memory comprises a three-dimensional memory.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: HAHN, JUDAH GAMLIEL; BAZARSKY, ALEXANDER; NAVON, ARIEL; GUR, DAVID
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045107/0681 →
Continuity (2)
Continuation In Part 15465367 · Mar 21, 2017
Related Publication 20180276116A1 · Sep 27, 2018
Cited By (2)
US 12,197,318 US 12,449,996