IP Library Granted Patent US 12,399,214
Granted Patent B2
US 12,399,214 · App. 17/654,257 · Granted Aug 26, 2025

Systems, devices, and methods for testing integrated circuits in their native environments

Inventors: Nadav Tsur (Bet Herut, IL); Avi Shani (Petach Tikva, IL); Yair Sommer (Even Yehuda, IL)
Assignee: Sandisk Technologies, Inc.
G01R31/2886B23K1/0016H05K1/0268H05K3/3436H05K3/363B23K2101/42H05K1/0393H05K1/111H05K1/115H05K1/14H05K1/18H05K2201/09127
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Quick Facts
Patent No.
US 12,399,214
App. No.
17/654,257
Granted
Aug 26, 2025
Kind
B2
Abstract

Disclosed herein are unitary printed circuit boards (PCBs) and methods of using them for testing an integrated circuit (IC). In some embodiments, a unitary PCB comprises a main board portion and a flexible PCB portion, which are configured to be detached from each other at a separation location on the unitary PCB. The main board portion comprises a plurality of pads, and the flexible PCB portion comprises a plurality of through-holes, where a layout of the through-holes corresponds to a layout of the plurality of pads. In some embodiments, a method of testing an IC of a device comprises separating the unitary PCB into a main board portion and a flexible PCB portion, attaching the IC to the main board portion, soldering the main board portion to a platform PCB of the device, and attaching the flexible PCB portion to the main board portion.

Claims (25)

1. A unitary printed circuit board (PCB) for testing an integrated circuit (IC), the unitary PCB comprising:

a main board portion on a first side of a separation line, the main board comprising a first plurality of pads; and

a flexible PCB portion on a second side of the separation line, the flexible PCB portion comprising:

a plurality of through-holes disposed on a first end of the flexible PCB portion; and

a plurality of connectors disposed on a second end of the flexible PCB portion, the plurality of connectors configured to connect the flexible PCB portion to an external test circuit, wherein:

the main board portion and the flexible PCB portion are configured to be detached from each other at the separation line,

a layout of the plurality of through-holes of the flexible PCB portion to matches a layout of the first plurality of pads of the main board portion, wherein the plurality of through-holes are configured to be aligned and soldered to the first plurality of pads.

2. The unitary PCB recited in claim 1 , wherein the main board portion further comprises a plurality of contact points, wherein a layout of the plurality of contact points matches a layout of a plurality of pins of the IC, and the plurality of contact points of the main board portion are configured to be coupled to the plurality of pins of the IC.

3. The unitary PCB recited in claim 2 , wherein the main board portion further comprises a plurality of transfer lines, and wherein at least subset of the plurality of contact points is coupled to the plurality of transfer lines for transferring signals from the IC.

4. The unitary PCB recited in claim 2 , wherein the soldering of the plurality of through-holes to the first plurality of pads is configured to connect the IC to an external test circuit.

5. The unitary PCB recited in claim 1 , wherein a thickness of the main board portion is less than approximately 0.5 mm.

6. The unitary PCB recited in claim 1 , wherein the main board portion further comprises a plurality of contact points, wherein a layout of the plurality of contact points matches a layout of a ball grid array of the IC, and the plurality of contact points are configured to be soldered in one operation in parallel to the ball grid array of the IC.

7. The unitary PCB recited in claim 1 , wherein the main board portion further comprises a second plurality of pads configured to connect the IC to an external test circuit.

8. The unitary PCB recited in claim 1 , wherein the main board portion comprises a universal flash storage (UFS) connector and/or a VSF connector.

9. The unitary PCB recited in claim 1 , wherein a size of the main board portion is approximately 20 mm by approximately 13 mm.

10. A method of using the unitary PCB recited in claim 2 , the method comprising:

separating the main board portion from the flexible PCB portion at the separation line;

soldering at least a portion of the plurality of pins of the IC to at least a portion of the plurality of contact points;

aligning the through-holes of the flexible PCB portion with the first plurality of pads of the main board portion; and

reattaching the flexible PCB portion to the main board portion by soldering at least a portion of the through-holes of the flexible PCB portion to a corresponding at least a portion of the first plurality of pads.

11. A method of using the unitary PCB recited in claim 1 , the method comprising:

separating the main board portion from the flexible PCB portion at the separation line;

soldering the IC to the main board portion;

aligning the through-holes of the flexible PCB portion with the first plurality of pads of the main board portion; and

reattaching the flexible PCB portion to the main board portion by soldering at least a portion of the through-holes of the flexible PCB portion to a corresponding at least a portion of the first plurality of pads.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2022
From: TSUR, NADAV; SHANI, AVI; SOMMER, YAIR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059220/0460 →
Continuity (2)
Provisional Application 63232127 · Aug 11, 2021
Related Publication 20230045808A1 · Feb 16, 2023
References Cited (10)
US 6859054B1 · Zhou et al. · 2005 [cited by applicant]
US 7068059B2 · Hanke et al. · 2006 [cited by applicant]
US 10269696B2 · Vreman et al. · 2019 [cited by applicant]
US 20060267615A1 · Grilletto · 2006 [cited by examiner]
US 20180164343A1 · Wang · 2018 [cited by examiner]
US 20190122974A1 · Goh et al. · 2019 [cited by applicant]
US 20200375028A1 · Lee · 2020 [cited by examiner]
US 20210008364A1 · Chen · 2021 [cited by examiner]
TW I244802B · 2005 [cited by applicant]
WO 2018089659A1 · 2018 [cited by applicant]