IP Library Granted Patent US 11,604,592
Granted Patent B2
US 11,604,592 · App. 17/339,547 · Granted Mar 14, 2023

Data management for efficient low power mode handling in a storage device

Inventors: Ramanathan Muthiah (Bangalore, IN); Lakshmi Sowjanya Sunkavelli (Bangalore, IN); Stella Achtenberg (Netanya, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/064G06F3/0625G06F3/0659G06F3/0679G06N5/022
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Quick Facts
Patent No.
US 11,604,592
App. No.
17/339,547
Granted
Mar 14, 2023
Kind
B2
Abstract

A method and apparatus for identifying data that is to be accessible in a low power state of a data storage device, and store this data in a physical (or logical) block that will be accessible in a low power state of the data storage device. Low power accessible data may be identified by host metadata of the data, indicating access is needed in a low power state. In other embodiments, the data storage device may learn the power state in which data should be accessible. In these embodiments, a controller stores information regarding the power state of a namespace in which the data is stored as an indicator to make the data accessible in a low power state. Alternatively, the controller stores a previous power state in which the data was accessed as an indicator to make the data accessible in a low power state.

Claims (44)

1. A data storage device, comprising:

a memory device comprising a plurality of blocks; and

a controller coupled to the memory device, the controller being configured to execute a method for data management for low power mode handling, the method comprising:

identifying a block of the plurality of blocks to remain active in a low power state of the data storage device;

receiving a first data element;

classifying the first data element to be accessible in the low power state of the data storage device; and

storing at least a portion of the first data element to the identified block, wherein classifying the first data element to be accessible in a low power state comprises identifying a previous power state in which the first data element was accessed.

2. The data storage device of claim 1 , wherein classifying the first data element to be accessible in a low power state comprises parsing metadata of the first data element, the metadata identifying the first data element as being accessible in the low power state.

3. The data storage device of claim 1 , wherein the previous power state in which the first data element was accessed was the low power state.

4. The data storage device of claim 1 , wherein classifying the first data element comprises identifying a logical namespace in which the first data element had been stored.

5. The data storage device of claim 4 , identifying the logical namespace as being accessible in the low power state.

6. A data storage device, comprising:

a memory device comprising a plurality of blocks; and

a controller coupled to the memory device, the controller being configured to execute a method for data management for low power mode handling, the method comprising:

identifying a block of the plurality of blocks to remain active in a low power state of the data storage device;

receiving a first data element;

classifying the first data element to be accessible in the low power state of the data storage device; and

storing at least a portion of the first data element to the identified block, wherein a flash translation layer (FTL) directs the portion of the first data element to the identified block.

7. A controller for a data storage device, comprising:

a memory device comprising firmware instructions; and

a processor coupled to the memory device and configured to execute the firmware instructions that cause the processor to:

classify a plurality of power states of the data storage device, comprising a first power state, a second power state, and a third power state being at a lower power state than the first power state and the second power state;

classify at least a portion of a second memory device coupled to the controller as being operational in the third power state;

receiving a first data element from a host;

identify the first data element as required to be available in the third power state; and

store the first data element in the portion of the second memory device classified as being operational in the third power state.

8. The controller of claim 7 , wherein the firmware instructions to identify the data element further cause the controller to identify a logical namespace in which the first data element had been stored previously.

9. The controller of claim 8 , wherein the logical namespace had been designated as being accessible in the third power state.

10. The controller of claim 7 , wherein the firmware instructions to identify the data element further cause the controller to identify a previous power state in which the first data element was accessible.

11. The controller of claim 10 , wherein the previous power state was the third power state.

12. The controller of claim 7 , wherein the firmware instructions to identify the data element further cause the controller to parse metadata of the first element, the metadata identifying the first data element as being accessible in the third power state.

13. The controller of claim 7 , further comprising additional processor-readable instructions that cause the controller to receive a second data element identified as being accessible in one of the first power state and second power state, and storing the second data element in a third memory device.

14. A data storage device, comprising:

a first memory means operational in a first power state;

a second memory means operational in a second power state that is different from the first power state; and

a controller means coupled to the first memory means and the second memory means, the controller means configured to:

receive a data element comprising a data element power state;

query a learning database indicating a power state in which the data element is used; and

responsive to querying the learning database and based on the data element power state, store the data element in one of the first memory means or second memory means.

15. The data storage device of claim 14 , wherein the learning database comprises a namespace to which the data element had been assigned in previously.

16. The data storage device of claim 15 , wherein the namespace had been accessible in one of the first power state or the second power state.

17. The data storage device of claim 14 , wherein the learning database comprises classification data classifying the data element as having been accessible in one of the first power state or the second power state.

18. The data storage device of claim 14 , wherein the data element comprises metadata indicating the data element is accessible in one of the first power state and the second power state.

19. The data storage device of claim 18 , wherein the metadata is set by a host.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2021
From: MUTHIAH, RAMANATHAN; SUNKAVELLI, LAKSHMI SOWJANYA; ACHTENBERG, STELLA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056445/0054 →