Geometry-aware command scheduling
Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
1. A storage system, comprising:
a memory organized into a plurality of memory sets, wherein a first memory set of the plurality of memory sets comprises a first memory portion; and
a controller configured to:
determine a command state of the first memory set;
queue an erase command to erase data stored in the first memory portion, when the first memory set is in a pending command state; and
schedule the erase command for execution to erase the data stored in the first memory portion, when a timer for the erase command has expired, and the first memory set remains in the pending command state.
2. The storage system of claim 1 , wherein the controller is configured to:
assign a write command, to a second memory portion of a plurality of memory portions of the memory, for writing data associated with the write command, wherein the first memory set comprises the first memory portion and the second memory portion;
when the scheduled erase command is pending for the first memory portion, re-assign the write command to write the data associated with the write command, to a memory portion in a second memory set of the plurality of memory sets, wherein the second memory set is different from the first memory set; and
schedule the write command to write the data associated with the write command.
3. The storage system of claim 2 , wherein the controller is configured to:
when the scheduled erase command is not pending for the first memory portion, schedule the write command using the second memory portion in the first memory set, to write the data associated with the write command; and
when the scheduled erase command is pending for the first memory portion, schedule the write command using the memory portion in the second memory set, to write the data associated with the write command.
4. The storage system of claim 1 , wherein the controller is configured to:
monitor the command state of the first memory set when the first memory set is determined to be in the pending command state; and
schedule the erase command queued in a wait queue to erase the data stored in the first memory portion, when the command state of the first memory set is changed from the pending command state to an idle command state.
5. The storage system of claim 1 , wherein the controller is configured to:
when the first memory set is determined to be in an idle command state, schedule the erase command to erase the data stored in the first memory portion.
6. The storage system of claim 1 , wherein the controller configured to determine the command state of the first memory set comprises the controller configured to determine whether a bit corresponding to the first memory set is set in a status data set.
7. The storage system of claim 1 , wherein a plurality of memory portions comprises the first memory portion, wherein the first memory set comprises the plurality of memory portions, wherein each memory set of the plurality of memory sets comprises a respective die in a respective one of a plurality of memory channels of the memory, and wherein each memory portion of the plurality of memory portions comprises a respective memory block in a respective die.
8. A machine-implemented method, comprising:
determining a command state of a first memory set of a plurality of memory sets of a memory, wherein the first memory set comprises a first memory portion;
queuing an erase command to erase data stored in the first memory portion of a plurality of memory portions of the memory, when the first memory set is in a pending command state; and
scheduling the erase command to erase the data stored in the first memory portion, when a timer for the erase command has expired, and the first memory set remains in the pending command state.
9. The machine-implemented method of claim 8 , comprising:
assigning a write command to a second memory portion of the plurality of memory portions for writing data associated with the write command, wherein the first memory set comprises the first memory portion and the second memory portion;
when the scheduled erase command is pending for the first memory portion, re-assigning the write command to write the data associated with the write command, to a memory portion in a second memory set of the plurality of memory sets, wherein the second memory set is different from the first memory set; and
scheduling the write command for execution to write the data associated with the write command.
10. The machine-implemented method of claim 9 , comprising:
when the scheduled erase command is not pending for the first memory portion, scheduling the write command using the second memory portion in the first memory set, to write the data associated with the write command; and
when the scheduled erase command is pending for the first memory portion, scheduling the write command using the memory portion in the second memory set, to write the data associated with the write command.
11. The machine-implemented method of claim 8 , comprising:
monitoring the command state of the first memory set when the first memory set is determined to be in the pending command state; and
scheduling the erase command queued in a wait queue to erase the data stored in the first memory portion, when the command state of the first memory set is changed from the pending command state to an idle command state.
12. The machine-implemented method of claim 8 , comprising:
when the first memory set is determined to be in an idle command state, scheduling the erase command to erase the data stored in the first memory portion.
13. The machine-implemented method of claim 8 , wherein determining the command state of the first memory set comprises determining whether a bit corresponding to the first memory set is set in a status data set.
14. The machine-implemented method of claim 8 , wherein each memory set of the plurality of memory sets comprises a respective die in a respective one of a plurality of memory channels of the memory, wherein each memory portion of a plurality of memory portions comprises a respective memory block in a respective die.
15. An apparatus, comprising:
means for determining a command state of a first memory set of a plurality of memory sets of a memory, wherein the first memory set comprises a first memory portion;
means for queuing an erase command to erase data stored in the first memory portion of a plurality of memory portions of the memory, when the first memory set is in a pending command state; and
means for scheduling the erase command to erase the data stored in the first memory portion, when a timer for the erase command has expired, and the first memory set remains in the pending command state.
16. The apparatus of claim 15 , comprising:
means for assigning a write command to a second memory portion of the plurality of memory portions for writing data associated with the write command, wherein the first memory set comprises the first memory portion and the second memory portion;
when the scheduled erase command is pending for the first memory portion, means for re-assigning the write command to a memory portion in a second memory set of the plurality of memory sets, wherein the second memory set is different from the first memory set; and
means for scheduling the write command for execution to write the data associated with the write command.
17. The apparatus of claim 15 , comprising:
means for monitoring the command state of the first memory set when the first memory set is determined to be in the pending command state; and
means for scheduling the erase command queued in a wait queue to erase the data stored in the first memory portion, when the command state of the first memory set is changed from the pending command state to an idle command state.
18. The apparatus of claim 15 , comprising:
when the first memory set is determined to be in an idle command state, means for scheduling the erase command to erase the data stored in the first memory portion.
19. The apparatus of claim 18 , wherein means for determining the command state of the first memory set comprises means for determining whether a bit corresponding to the first memory set is set in a status data set.
20. The apparatus of claim 15 , wherein each memory set of the plurality of memory sets comprises a respective die in a respective one of a plurality of memory channels of the memory, and wherein each memory portion of the plurality of memory portions comprises a respective memory block in a respective die.