IP Library Granted Patent US 11,467,744
Granted Patent B2
US 11,467,744 · App. 16/885,160 · Granted Oct 11, 2022

System to identify aggressor blocks causing back to back erase failure

Inventors: Nikhil Arora (Karnataka, IN); Lovleen Arora (Karnataka, IN); Sourabh Sankule (Karnataka, IN); Sameer Hiware (Karnataka, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/064G06F3/0604G06F3/0652G06F3/0673
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Quick Facts
Patent No.
US 11,467,744
App. No.
16/885,160
Granted
Oct 11, 2022
Kind
B2
Abstract

Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.

Claims (30)

1. A storage device, comprising:

a memory comprising non-volatile memory; and

a controller configured to:

program an open block of the non-volatile memory,

perform an attempt to erase a plurality of closed blocks of the non-volatile memory after programming of the open block,

determine a number of consecutive erase failures based on the attempt to erase the plurality of closed blocks, and

identify the open block as a bad block when the number of consecutive erase failures meets a threshold, wherein the open block identified as the bad block is a common open block between a plurality of lists of open blocks that are stored in the non-volatile memory.

2. The storage device of claim 1 , wherein the controller is further configured to perform a re-attempt to erase the plurality of closed blocks, and to identify the open block as the bad block when at least one of the plurality of closed blocks is successfully erased in response to the re-attempt.

3. The storage device of claim 2 , wherein the controller is further configured to store the plurality of lists of open blocks in an array of open blocks within the non-volatile memory after a plurality of attempts to erase the plurality of closed blocks.

4. The storage device of claim 1 , wherein the controller is further configured to store a first list of the plurality of lists of open blocks in the non-volatile memory after a first attempt to erase the plurality of closed blocks following a first programming of the open block, and wherein the controller is further configured to store a second list of the plurality of lists of open blocks in the non-volatile memory after a second attempt to erase the plurality of closed blocks following a second programming of the open block.

5. The storage device of claim 4 , wherein the controller is further configured to identify the common open block between the first list and the second list.

6. The storage device of claim 5 , wherein the controller is further configured to identify the common open block as the bad block in response to a determination that another common open block does not exist between the first list and the second list.

7. The storage device of claim 1 , wherein the controller is further configured to update an erase failure counter indicating the number of consecutive erase failures before identifying the open block as the bad block.

8. The storage device of claim 7 , wherein the controller is further configured to reset the erase failure counter after identifying the open block as the bad block.

9. A storage device, comprising:

a memory comprising non-volatile memory; and

a controller configured to program an open block of the non-volatile memory a plurality of times, to perform an attempt to erase a plurality of closed blocks of the non-volatile memory after each of the plurality of times, and to identify the open block as a bad block when a number of consecutive erase failures after programming the open block meets a threshold after each of the plurality of times, wherein the open block identified as the bad block is a common open block between a plurality of lists of open blocks that are stored in the non-volatile memory.

10. The storage device of claim 9 , wherein the controller is further configured to perform a re-attempt to erase the plurality of closed blocks after each of the plurality of times, and to identify the open block as the bad block when at least one of the plurality of closed blocks is successfully erased in response to the re-attempt after each of the plurality of times.

11. The storage device of claim 10 , wherein the controller is further configured to store at least one of the plurality of lists of open blocks in the non-volatile memory after each successful re-attempt to erase the plurality of closed blocks.

12. The storage device of claim 9 , wherein the controller is further configured to store a first list of the plurality of lists of open blocks in the non-volatile memory after one of the plurality of times, and wherein the controller is further configured to store a second list of the plurality of lists of open blocks in the non-volatile memory after another of the plurality of times.

13. The storage device of claim 12 , wherein the controller is further configured to identify the common open block between the first list and the second list after multiple attempts to erase the plurality of closed blocks.

14. A storage device, comprising:

a memory comprising non-volatile memory; and

a controller configured to program an open block of the non-volatile memory a number of times, to perform an attempt to erase a plurality of closed blocks of the non-volatile memory the number of times, and to identify the open block as a bad block when the attempt to erase the plurality of closed blocks fails the number of times, wherein the open block identified as the bad block is a common open block between a plurality of lists of open blocks that are stored in the non-volatile memory.

15. The storage device of claim 14 , wherein the controller is further configured to perform a re-attempt to erase the plurality of closed blocks the number of times, and to identify the open block as the bad block when at least one of the plurality of closed blocks is successfully erased in response to the re-attempt the number of times.

16. The storage device of claim 15 , wherein the controller is further configured to store the plurality of lists of open blocks in the non-volatile memory after successfully re-attempting to erase the plurality of closed blocks the number of times.

17. The storage device of claim 15 , wherein the controller is further configured to store a first list of the plurality of lists of open blocks in the non-volatile memory after one successful re-attempt to erase the plurality of closed blocks, and wherein the controller is further configured to store a second list of the plurality of lists of open blocks in the non-volatile memory after another successful re-attempt to erase the plurality of closed blocks.

18. The storage device of claim 17 , wherein the controller is further configured to identify the common open block between the first list and the second list, and to identify the common open block as the bad block when another common open block does not exist between the first list and the second list.

19. The storage device of claim 14 , wherein the controller is further configured to update an erase failure counter indicating a number of consecutive erase failures in response to the attempt to erase the plurality of closed blocks failing the number of times.

20. The storage device of claim 19 , wherein the controller is further configured to reset the erase failure counter in response to identifying the open block as the bad block.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2020
From: ARORA, NIKHIL; ARORA, LOVLEEN; SANKULE, SOURABH; HIWARE, SAMEER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053322/0006 →
Continuity (1)
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