IP Library Granted Patent US 10,001,924
Granted Patent B2
US 10,001,924 · App. 15/062,456 · Granted Jun 19, 2018

Efficient and dynamically sized reverse map to handle variable size data

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Quick Facts
Patent No.
US 10,001,924
App. No.
15/062,456
Granted
Jun 19, 2018
Kind
B2
Abstract

A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.

Claims (51)

1. A method comprising:

receiving a data stream including one or more data blocks;

determining a size of the one or more data blocks;

determining a number of mappings based on the size of the one or more data blocks and a size of a physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks stored in the physical block;

retrieving a dynamically sized reverse map, a size of the dynamically sized reverse map corresponding to the variable number of mappings for different physical blocks;

determining a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and

creating an entry for the physical block in the dynamically sized reverse map, the entry including the number of mappings of the physical block and the starting location for the one or more data blocks, the entry being an index of the numbers of mappings for the physical block.

2. The method of claim 1 , wherein dynamically sized reverse map includes a dynamic tree structure having an extensible node for a plurality of buffer entries, one buffer entry for each of the one or more data blocks.

3. The method of claim 1 , further comprising creating, a buffer entry for each of the one or more data blocks, the buffer entry including a logical block number, a physical block number, a starting sector in the physical block, and a number of sectors occupied in the physical block.

4. The method of claim 3 , wherein the buffer entry is persisted to a storage device.

5. The method of claim 4 , wherein the number of mappings of the physical block represents a number of buffer entries a physical block consumes.

6. The method of claim 3 , wherein the number of sectors occupied in the physical block is determined based on the size of each of the one or more data blocks and a size of the sectors.

7. The method of claim 1 , further comprising:

receiving a request to copy a plurality of data blocks from a first range of logical address to a second range of logical address;

determining a size of the plurality of data blocks;

determining number of references the plurality of data blocks occupy based on the size of the plurality of data blocks;

determining a forward pointer based on the dynamically sized reverse map for the plurality of data blocks; and

updating the dynamically sized reverse map with an extra entry with the forward pointer and the number of references.

8. The method of claim 1 , further comprising:

retrieving information of a map segment from a segment header;

determining a use count of write blocks of the map segment;

determining whether the map segment satisfies dynamically sized reverse map updating criteria based on the use count of the map segment;

responsive to the map segment satisfying the dynamically sized reverse map updating criteria, performing dynamically sized reverse map updating on the map segment; and

updating the information of the map segment in the segment header.

9. The method of claim 8 , wherein the map segment stores the dynamically sized reverse map.

10. A system comprising:

a dynamically sized reverse map having a variable size corresponding to a variable number of mappings for different physical blocks of a storage device; and

a processor coupled to the dynamically sized reverse map, the processor configured to:

receive a data stream including one or more data blocks;

determine a size of the one or more data blocks;

determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block;

determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and

create an entry for the physical block in the dynamically sized reverse map, the entry including the number of mappings of the physical block and the starting location for the one or more data blocks, the entry being an index of the variable numbers of mappings for the physical block.

11. The system of claim 10 , wherein the dynamically sized reverse map includes a dynamic tree structure having an extensible node for a plurality of buffer entries, one buffer entry for each of the one or more data blocks.

12. The system of claim 11 , wherein the extensible node includes buffer entry for each of the one or more data blocks, the buffer entry including a logical block number, a physical block number, a starting sector in the physical block, and a number of sectors occupied in the physical block.

13. The system of claim 12 , wherein the processor is configured to persist the buffer entry to a storage device.

14. The system of claim 13 , wherein the number of mappings of the physical block represents a number of buffer entries a physical block consumes.

15. The system of claim 12 , wherein the number of sectors occupied in the physical block is determined based on the size of each of the one or more data blocks and a size of the sectors.

16. The system of claim 10 , wherein the processor is further configured to:

receive a request to copy a plurality of data blocks from a first range of logical address to a second range of logical address;

determine a size of the plurality of data blocks;

determine number of references the plurality of data blocks occupy based on the size of the plurality of data blocks;

determine a forward pointer based on the dynamically sized reverse map for the plurality of data blocks; and

update the dynamically sized reverse map with an extra entry with the forward pointer and the number of references.

17. The system of claim 10 , wherein the processor is further configured to:

retrieve information of a map segment from a segment header;

determine a use count of write blocks of the map segment;

determine whether the map segment satisfies dynamically sized reverse map updating criteria based on the use count of the map segment;

responsive to the map segment satisfying the dynamically sized reverse map updating criteria, perform dynamically sized reverse map updating on the map segment; and

updating the information of the map segment in the segment header.

18. The system of claim 17 , wherein the map segment stores the dynamically sized reverse map.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2016
From: SHARMA, SANDEEP; MANCHANDA, SAURABH
To: HGST NETHERLANDS B.V.
Reel/Frame 039103/0632 →
Cited By (1)
US 12,423,011