IP Library Granted Patent US 11,615,805
Granted Patent B2
US 11,615,805 · App. 17/455,839 · Granted Mar 28, 2023

Zoned block command to stream command translator

Inventors: Darin Edward Gerhart (Oronoco, MN); Nicholas Edward Ortmeier (Rochester, MN); Cory Lappi (Rochester, MN); William Jared Walker (Rochester, MN)
Assignee: Western Digital Technologies, Inc.
G11B5/09G11B5/012
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Quick Facts
Patent No.
US 11,615,805
App. No.
17/455,839
Granted
Mar 28, 2023
Kind
B2
Abstract

A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Claims (31)

1. A computer system, comprising:

a memory arrangement, wherein the computer system is configured to:

receive a command at a layer of the computer system; and

convert the command received at the layer to a command type capable of operation in the memory arrangement when the type of command received at the layer is different than a type of command that is able to be received and is capable of operation in the memory arrangement, wherein the converting comprises converting a zone block command to a stream command.

2. The computer system of claim 1 , wherein the layer of the computer system is within a host system.

3. The computer system of claim 1 , wherein the layer of the computer system is within an SAS expander.

4. The computer system of claim 1 , wherein the layer of the computer system is in the memory arrangement.

5. The computer system of claim 1 , wherein the layer is a z-stream translator.

6. The computer system of claim 5 , wherein the z-stream translator comprises a write zone manager.

7. The computer system of claim 1 , wherein the memory arrangement is a solid state drive.

8. The computer system of claim 1 , wherein the computer system is further configured to:

transmit the command type capable of operation for the memory arrangement to the memory arrangement.

9. The computer system of claim 1 , wherein the computer system is further configured to:

receive the command type capable of operation for the memory arrangement at the memory arrangement.

10. A computer system, comprising:

a memory arrangement, wherein the computer system is configured to:

prepare an interface between a host system and the memory arrangement such that commands provided by the host system will be accepted and operated upon by the memory arrangement, wherein the accepted and operated comprises converting a zone block command to a stream command.

11. The computer system of claim 10 , wherein the interface between the host system and the memory arrangement provides at least one of data and commands from the memory arrangement such that the host system will be capable of accepting the data and acting upon the commands from the memory arrangement.

12. The computer system of claim 10 , wherein the memory arrangement comprises a z-stream translator.

13. The computer system of claim 12 , wherein the z-stream translator comprises a z-state machine.

14. The computer system of claim 12 , wherein the z-stream translator comprises a z-command handler.

15. The computer system of claim 12 , wherein an abstraction layer presents the interface of the memory arrangement to the host system as a device compliant for memory storage with the host system.

16. A computer system, comprising:

a memory arrangement, wherein the computer system is configured to:

receive a command at a layer of the computer system; and

process the command at the layer of the computer system, wherein the processing comprises converting a zone block command to a stream command.

17. The computer system of claim 16 , wherein the processing the command occurs in a component of the memory arrangement.

18. The computer system of claim 17 , wherein the component is a Z stream translator.

19. The computer system of claim 16 , wherein the memory arrangement is a solid state drive.

20. The computer system of claim 16 , wherein the computer system is further configured to:

transmit the command to the memory arrangement.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2021
From: GERHART, DARIN EDWARD; ORTMEIER, NICHOLAS EDWARD; LAPPI, CORY; WALKER, WILLIAM JARED
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058169/0463 →