Method and system for identifying erased memory areas
View Patent ↗The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.
1. A data storage system, comprising:
a memory; and
a controller configured to:
provide a first codeword, from a page of the memory, to a first decoder for decoding;
when the first codeword is not decodable, identify the page as being in a programmed state; and
when the first codeword is successfully decoded:
provide first decoded data of the first decoder to a second decoder for verification;
when the first decoded data is verified, identify the page as being in the programmed state; and
when the first decoded data is not verified, identify the page as being in an erased state.
2. The data storage system of claim 1 , wherein the controller is configured to:
configure the first decoder to operate in a scanning configuration, wherein codewords having all bits in a first logical value are decodable by the first decoder operating in the scanning configuration.
3. The data storage system of claim 2 , wherein the controller is configured to:
configure the second decoder to operate in the scanning configuration, wherein the codewords having all bits in the first logical value are not verifiable by the second decoder operating in the scanning configuration.
4. The data storage system of claim 3 , wherein the scanning configuration of the first and second decoders is different from a writing configuration used to encode data for writing to the memory.
5. The data storage system of claim 1 , wherein the first decoder is an error-correcting code decoder, and the second decoder is an error-detecting decoder.
6. The data storage system of claim 4 , wherein the first decoder is a low-density parity-check decoder.
7. The data storage system of claim 1 ,
wherein the memory comprises a plurality of blocks, and
wherein for each block of the plurality of blocks, the controller is configured to receive a respective first codeword from a respective page of the respective block and provide respective first decoded data when the respective first codeword is successfully decoded.
8. The data storage system of claim 7 , wherein for each block of the plurality of blocks, the controller is configured to:
receive a respective second codeword read from the respective page of the respective block;
provide the respective second codeword to the first decoder for decoding;
receive either a success indicator from the first decoder when the respective second codeword is successfully decoded or a failure indicator from the first decoder when the respective first codeword or the respective second codeword is not decodable,
identify the respective page as being in the programmed state when the failure indicator is received from the first decoder for either the respective first codeword or the respective second codeword;
when the success indicator is received from the first decoder:
provide respective second decoded data from the first decoder to the second decoder for verification;
receive either a success indicator from the second decoder when the respective second decoded data is verified or a failure indicator from the second decoder when the respective second decoded data is not verified;
identify the respective page as being in the programmed state when the success indicator is received from the second decoder for either the respective first decoded data or the respective second decoded data; and
identify the respective page as being in the erased state when the failure indicator is received from the second decoder for both the respective first decoded data and the respective second decoded data.
9. A machine-implemented method, comprising:
providing a first codeword, from a page of a memory, to a first decoder for decoding;
when the first codeword is not decodable, identifying the page as being in a programmed state; and
when the first codeword is successfully decoded:
providing first decoded data of the first decoder to a second decoder for verification; and
when the first decoded data is not verified, identifying the page as being in an erased state,
wherein the identifying facilitates determining a last programmed page in a block of the memory without incurring additional time and processing during a soft decoding operation performed in response to a hard decode failure.
10. The machine-implemented method of claim 9 , comprising:
configuring the first decoder to operate in a scanning configuration, wherein codewords having all bits at a first logical value are decodable by the first decoder operating in the scanning configuration.
11. The machine-implemented method of claim 10 , comprising:
configuring the second decoder to operate in the scanning configuration, wherein the codewords having all bits at the first logical value are not verifiable by the second decoder operating in the scanning configuration.
12. The machine-implemented method of claim 9 , wherein the first decoder is an error-correcting code decoder and the second decoder is an error-detecting decoder.
13. The machine-implemented method of claim 9 , wherein the first decoder is a low-density parity-check decoder.
14. The machine-implemented method of claim 11 , wherein the scanning configuration of the first and second decoders is different from a writing configuration used to encode data for writing to the memory.
15. The machine-implemented method of claim 9 , comprising:
receiving a first success indicator from the first decoder when the first codeword is successfully decoded by the first decoder;
receiving a first failure indicator from the second decoder when the first decoded data is not verified by the second decoder;
receiving a second codeword read from the page of the memory;
providing the second codeword to the first decoder for decoding;
receiving a second success indicator from the first decoder when the second codeword is successfully decoded;
providing second decoded data from the first decoder to the second decoder for verification of the second decoded data in response to receiving the second success indicator; and
receiving a second failure indicator from the second decoder when the second decoded data is not verified,
wherein the page is identified as being in the erased state based on receiving both the first and second success indicators and both the first and second failure indicators.
16. The machine-implemented method of claim 15 , wherein the page is not identified as being in the erased state based on not receiving at least one of the following: the first success indicator, the second success indicator, the first failure indicator, or the second failure indicator.
17. A data storage system, comprising:
a memory;
means for decoding a first codeword received from a page of the memory;
means for verifying decoded data of the first codeword; and
means for identifying the page of the memory as being in an erased state when the means for decoding the first codeword successfully decodes the first codeword and the means for verifying the decoded data does not verify the decoded data,
wherein the means for identifying is configured to facilitate determining a last programmed page in a block of the memory without incurring additional time and processing during a soft decoding operation performed in response to a hard decode failure.
18. The data storage system according to claim 17 , comprising:
means for configuring the means for decoding to operate in a scanning configuration, wherein codewords having all bits in a first logical value are decodable by the means for decoding operating in the scanning configuration; and
means for configuring the means for verifying to operate in the scanning configuration, wherein the codewords having all bits in the first logical value are not verifiable by the means for verifying operating in the scanning configuration.
19. The data storage system of claim 17 , comprising means for identifying the page as being in a programmed state when either the means for decoding is unsuccessful in decoding the first codeword or the means for verifying verifies the decoded data.
20. The data storage system of claim 17 , wherein the means for decoding comprises means for performing error correction, and the means for verifying comprises means for performing error detection.