Semiconductor device including through-package debug features
A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.
1. A method of debugging a semiconductor device mounted on a host device, the semiconductor device comprising a substrate, a semiconductor die and a housing, the method comprising:
(a) forming the substrate with a first surface and a second surface opposed to the first surface;
(b) forming the housing with a thickness, greater than a thickness of the semiconductor die, the thickness defined by a first surface and a second surface spaced from the first surface, the second surface lying against the first surface of the substrate;
(c) forming an electrically conductive debug feature having a first end at the first surface of the housing, and the debug feature having a second end terminating at a test pad formed in the first surface of the substrate, wherein the debug feature comprises an electrically conductive test pin, and the step of forming the electrically conductive test pin comprising the steps of:
(c1) drilling a hole in the housing, and
(c2) after said step (c1), forming an electrically conductive material on the wall of the drilled hole;
(d) forming a trace in the substrate between the semiconductor die and the test pad for electrically coupling the test pad to the semiconductor die;
(e) spacing the first end of the debug feature, at the first surface of the housing, from the substrate;
(f) physically contacting a surface probe to the first end of the electrically conductive debug feature on the housing to supply test data to circuitry within the semiconductor device via the probe and the test pad; and
(g) measuring output data resulting from the test data.
2. The method of claim 1 , wherein said step (c) of electrically coupling the probe with a test pad within the semiconductor device comprises positioning the probe in contact with the debug feature on the surface of the housing of the semiconductor device.
3. The method of claim 1 , said step (f) of electrically contacting a surface probe to the first end of the electrically conductive debug feature comprises positioning the probe in contact with the test pin on the surface of the housing of the semiconductor device.
4. The method of claim 1 , wherein said step (c2) of forming an electrically conductive material on the wall of the drilled hole comprises plating the hole with an electrical conductor.
5. The method of claim 4 , further comprising the step of forming the debug feature by filling the plated hole with an electrically conductive metal.
6. A method of assembling a semiconductor device for debugging with a controller die within the semiconductor device, comprising:
(a) forming a substrate within the semiconductor device, the substrate having a first surface and a second surface opposed to the first surface;
(b) mounting a plurality of semiconductor dies on the first surface of the substrate, the plurality of semiconductor dies comprising the controller die;
(c) forming a test pad within the semiconductor device;
(d) electrically coupling the test pad to the controller die;
(e) forming a housing with a thickness greater than a thickness of the plurality of semiconductor dies to encapsulate the test pad and the plurality of semiconductor dies, the housing having an internal surface lying against the first surface of the substrate and an external surface coextensive with an external surface of the semiconductor device; and
(f) forming an electrical conductor extending upward from the test pad and terminating at the external surface of the housing spaced from the substrate, the electrical conductor configured for use in debugging the semiconductor device.
7. The method of claim 6 , wherein said steps (c) and (d) of forming a test pad and electrically coupling the test pad to the controller die comprises the steps of forming the test pad on the substrate, and electrically coupling the test pad to the controller die by electrical traces in the substrate.
8. The method of claim 6 , wherein said steps (c) and (d) of forming a test pad and electrically coupling the test pad to the controller die comprises the step of forming the test pad on a surface of the controller die.
9. The method of claim 6 , the step (f) of forming the electrical conductor extending from the test pad comprising the step of drilling a hole through the housing down to the test pad within the housing on the substrate, and plating and/or filling the hole with an electrical conductor.
10. The method of claim 6 , the step (f) of forming the electrical conductor extending from the test pad comprising the steps of forming an electrically conductive column having a first end affixed to the test pad and extending upward from the test pad, and forming housing around the electrically conductive column, the electrically conductive column terminating at a surface of the housing.