Data shaping for integrated memory assembly
A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.
1. An apparatus, comprising:
a first semiconductor die comprising non-volatile memory cells and a first plurality of pathways; and
a second semiconductor die directly bonded to the first semiconductor die, the second semiconductor die comprising one or more control circuits, an interface to a memory controller and a second plurality of pathways, the one or more control circuits are configured to transfer signals to the first semiconductor die through pathway pairs of the first plurality of pathways and the second plurality of pathways, the interface to the memory controller is separate from and different than the pathway pairs, the pathway pairs provide a wider interface than the interface to the memory controller, the one or more control circuits on the second semiconductor die are configured to:
receive a request to program data on the first semiconductor die, the request is received from the memory controller via the interface to the memory controller,
receive the data to be programmed from the memory controller via the interface to the memory controller,
on the second semiconductor die, encode the data to include error correction information,
on the second semiconductor die, shape the data to create shaped data, and
program the encoded and shaped data to a set of non-volatile memory cells on the first semiconductor die.
2. The apparatus of claim 1 , wherein:
the data comprises a first set of bits, each bit of the first set of bits corresponds to a logical value of a set of logical values, the set of logical values includes a first logical value and a second logical value; and
the one or more control circuits are configured to shape the data by applying a shaping operation to the first set of bits to generate a second set of bits, where a proportion of bits in the second set of bits having the first logical value is larger for the second set of bits than for the first set of bits.
3. The apparatus of claim 1 , wherein:
the data is part of a set of information being programmed to the first semiconductor die;
the data comprises a first set of bits; and
the one or more control circuits are configured to shape the data by dynamically selecting a mapping rule based on the set of information being programmed and applying the selected mapping rule to the first set of bits to map the first set of bits to a second set of bits.
4. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to encode the data by encoding the shaped data to include error correction information and form a codeword, the codeword includes data bits and parity bits;
the one or more control circuits are configured to rotate bits of the codeword to change position of the parity bits; and
the one or more control circuits are configured to program the encoded and shaped data by programming the codeword after the bits are rotated.
5. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to encode the data to include error correction information and form a codeword;
the one or more control circuits are configured to shape the data by shaping the codeword to form a shaped codeword; and
the one or more control circuits are configured to program the encoded and shaped data by programming the shaped codeword.
6. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to select a number of parity bits, the one or more control circuits are configured to encode the data to include error correction information by adding the number of parity bits to the data to form a codeword.
7. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to dynamically select a number of parity bits based on a number of program operations previously performed by the first semiconductor die, the one or more control circuits are configured to encode the data to include error correction information by adding the number of parity bits to the data to form a codeword.
8. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to select a number of parity bits based on a number of pathway pairs, the one or more control circuits are configured to encode the data to include error correction information by adding the number of parity bits to the data to form a codeword.
9. The apparatus of claim 1 , wherein:
the data to be programmed that is received from the memory controller via the interface to the memory controller includes user data, without including error correction data and without shaping.
10. The apparatus of claim 1 , wherein:
the first semiconductor die includes a non-volatile memory array; and
the second semiconductor die includes sense amplifiers for reading data from the non-volatile memory array on the first semiconductor die.
11. The apparatus of claim 10 , wherein:
the non-volatile memory array includes word lines;
the second semiconductor die includes address decoders for the non-volatile memory array on the first semiconductor die; and
the second semiconductor die includes signal generators configured to generate voltages applied to the word lines of the non-volatile memory array on the first semiconductor die to program the encoded and shaped data.
12. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to program the encoded and shaped data to a set of non-volatile memory cells on the first semiconductor die by transmitting each bit of the encoded and shaped data to the first semiconductor die via a different pathway pair the plurality of pathways.
13. The apparatus of claim 1 , wherein the one or more control circuits are configured to:
read the shaped codeword from the first semiconductor die;
remove shaping from the shaped codeword to from a de-shaped codeword;
decode the de-shaped codeword, the de-shaped codeword includes data bits and parity bits; and
transfer the data bits to the memory controller without transferring the parity bits to the memory controller.
14. The apparatus of claim 1 , wherein the one or more control circuits are configured to:
read the shaped codeword from the first semiconductor die;
rotate bits of the shaped codeword to restore parity bits of the codeword to their original position;
decode the rotated shaped codeword to form decoded shaped data;
remove shaping from the decoded shaped data to from output data bits; and
transfer the output data bits to the memory controller without transferring the parity bits to the memory controller.
15. The apparatus of claim 1 , wherein:
the non-volatile memory cells are organized into multiple partitions, each partition is assigned to a different shaping level;
the one or more control circuits on the second semiconductor die are configured to choose a shaping level for the data;
the one or more control circuits on the second semiconductor die are configured to program the encoded and shaped data to a partition of the multiple partitions that is assigned to the chosen shaping level; and
the partition of the multiple partitions that is assigned to the chosen shaping level includes the set of non-volatile memory cells on the first semiconductor die.
16. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to program the encoded and shaped data to the set of non-volatile memory cells on the first semiconductor die as SLC data;
the one or more control circuits are configured to program additional data as additional encoded and shaped data to non-volatile memory cells on the first semiconductor die as SLC data; and
the one or more control circuits are further configured to:
access, decode, correct one or more errors and remove shaping from the encoded and shaped data that is stored on the first semiconductor die as SLC data,
access, decode, correct one or more errors and remove shaping from the additional encoded and shaped data that is stored on the first semiconductor die as SLC data,
combine the data and additional data to form combined MLC data,
shape the combined MLC data to form shaped MLC data, and
program the shaped MLC data on the first semiconductor die.
17. A method, comprising:
a memory controller receiving data from a host that is separate from the memory controller;
the memory controller transferring the data to an integrated assembly comprising a control die bonded to a memory die;
receiving the data at the control die from the memory controller;
at the control die, selecting a number of parity bits;
at the control die, encoding the data to include error correction information and form a codeword that includes the selected number of parity bits, the codeword comprises a first set of bits, each bit of the first set of bits corresponds to a logical value of a set of logical values, the set of logical values includes a first logical value and a second logical value;
at the control die, shaping the codeword to create a shaped codeword by applying a shaping operation to the first set of bits to generate a second set of bits, where a proportion of bits in the second set of bits having the first logical value is larger for the second set of bits than for the first set of bits; and
programming the shaped codeword on the memory die.
18. The process of claim 17 , further comprising:
choosing a mapping rule from a plurality of mapping rules based on a set of information being programmed to the memory die, the shaping operation comprises applying the mapping rule to the codeword to generate the second set of bits.
19. The process of claim 17 , wherein:
the data received at the control die from the memory controller includes user data without including parity bits.
20. A non-volatile storage apparatus, comprising:
a memory controller configured to communicate with a host, the memory controller is separate from the host; and
an integrated memory assembly connected to the memory controller, the integrated memory assembly comprises a memory die and a control die directly bonded to the memory die, the memory die includes non-volatile memory cells;
the memory controller is configured to encode data by adding a first number of parity bits, the control die is configured to encode data by adding a second number of parity bits, the second number of parity bits is greater than the first number of parity bits;
the memory controller is configured to transfer first data to the control die;
the memory controller is configured to request that the first data be programmed on the memory die,
the control die is configured to:
encode the first data to add error correction information and form a codeword, the codeword comprises a first set of bits, each bit of the first set of bits corresponds to a logical value of a set of logical values, the set of logical values includes a first logical value and a second logical value,
shape the codeword to create a shaped codeword by applying a shaping operation to the first set of bits to generate a second set of bits, where a proportion of bits in the second set of bits having the first logical value is larger for the second set of bits than for the first set of bits, and
program the shaped codeword on the memory die.
21. The non-volatile storage apparatus of claim 20 , wherein:
the first set of bits comprises data bits and parity bits; and
the first data that is transferred from the memory controller to the control die includes the data bits without including the parity bits.
22. The non-volatile storage apparatus of claim 20 , wherein:
the non-volatile memory cells comprise a non-volatile memory array;
the non-volatile memory array includes word lines and bit lines;
the control die includes sense amplifiers for reading data from the non-volatile memory array on the memory die, the sense amplifiers are connected to the bit lines; and
the control die includes a signal generator configured to generate a voltage applied to one or more of the word lines to program the shaped codeword.
23. The apparatus of claim 1 , wherein:
the first semiconductor die includes a first set of bond pads;
the second semiconductor die includes a second set of bond pads bonded to the first set of bond pads to directly bond the second semiconductor die to the first semiconductor die,
the first plurality of pathways include the first set of bond pads; and
the one or more control circuits are configured to transfer the encoded and shaped data to the first semiconductor die for programming into the set of non-volatile memory cells on the first semiconductor die through pathway pairs of the first plurality of pathways and the second plurality of pathways via the first set of bond pads and the second set of bond pads such that each bit of the encoded and shaped data is transferred via a different bond pad of the second set of bond pads.