Resistive memory device by substrate reduction
View Patent ↗To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.
1. A solid state data storage array, comprising:
resistive random access memory (ReRAM) elements connected in series by metallized interconnect, the metallized interconnect comprising metallizing material introduced between adjacent ReRAM elements to establish a conductive link between the adjacent ReRAM elements;
each of the ReRAM elements comprising an active zone between a source and drain, the active zone comprising resistive memory material formed into a layer of a substrate by altering a chemical reduction level of the substrate, with resistance properties of the resistive memory material corresponding to data stored by an associated ReRAM element;
each of the ReRAM elements further comprising an isolation layer formed into the active zone by chemical oxidation of a layer of the active zone, wherein the substrate has a first surface and a second surface opposite the first surface and a third surface opposite the first surface, wherein the active zone has a fourth surface and a fifth surface opposite the fourth surface and the fourth surface is in contact with the second surface, wherein the fifth surface is below the third surface, wherein the isolation layer has a sixth surface and a seventh surface opposite the sixth surface and the sixth surface is in contact with the fifth surface, and wherein the seventh surface is above the third surface; and
each of the ReRAM elements further comprising a gate portion positioned proximate to the isolation layer and configured to alter the resistance properties of the active zone responsive to at least voltages applied to the gate portion.
2. The solid state data storage array of claim 1 , wherein the active zone comprises a partially reduced region in a layer of the substrate, and wherein the source and drain each comprise a region of the substrate reduced further than the active zone to establish a conductive property in the substrate.
3. The solid state data storage array of claim 1 , wherein the isolation layer is configured to inhibit migration of contaminants into a surface of the active zone.
4. The solid state data storage array of claim 1 , wherein a material of the substrate comprises at least one of an oxide of titanium, oxide of hafnium, oxide of tantalum, oxide of zirconium, oxide of tungsten, oxide of ruthenium, oxide of yttrium, oxide of scandium, oxide of cobalt, oxide of nickel, oxide of copper, perovskite material, and delafossite material.
5. A resistive memory storage device comprising:
a first memory element comprising:
an active channel disposed between a source and drain, the active channel comprising resistive memory material formed into a layer of a substrate by altering a chemical reduction level of the substrate with resistance properties;
an isolation layer formed into the active channel by chemical oxidation of a layer of the active channel, wherein the substrate has a first surface and a second surface opposite the first surface and a third surface opposite the first surface, wherein the active channel has a fourth surface and a fifth surface opposite the fourth surface and the fourth surface is in contact with the second surface, wherein the fifth surface is below the third surface, wherein the isolation layer has a sixth surface and a seventh surface opposite the sixth surface and the sixth surface is in contact with the fifth surface, and wherein the seventh surface is above the third surface; and
a gate portion positioned proximate to the isolation layer; and
a control system coupled with the first memory element through a first communication link coupled to the gate portion of the first memory element, the control system is configured to:
apply a first voltage via the communication link to the gate portion of the first memory element to alter the resistance property of the resistive memory material to store a first data bit in the first memory element.
6. The resistive memory storage device of claim 5 further comprising:
a second memory element connected in series with the first memory element by a metallized interconnect disposed the substrate.
7. The resistive memory storage device of claim 6 , wherein the control system is further configured to:
measure a series resistance of the first memory element and the second memory element.
8. The resistive memory storage device of claim 5 , wherein the control system is further configured to:
measure the resistance of the first memory element via the communication link.
9. A control system for a memory storage device, the control system comprising:
means for writing data into resistive memory elements connected in series by metallized interconnects disposed between adjacent memory elements by altering a resistance property of the memory elements reflective of the data, each of the memory elements comprising:
an active channel disposed between a source and a drain and comprising resistive memory material formed into a layer of a substrate by altering a chemical reduction level of the substrate;
an isolation layer formed into the active channel by chemical oxidation of a layer of the active channel, wherein the substrate has a first surface and a second surface opposite the first surface and a third surface opposite the first surface, wherein the active channel has a fourth surface and a fifth surface opposite the fourth surface and the fourth surface is in contact with the second surface, wherein the fifth surface is below the third surface, wherein the isolation layer has a sixth surface and a seventh surface opposite the sixth surface and the sixth surface is in contact with the fifth surface, and wherein the seventh surface is above the third surface; and
a gate portion positioned proximate the isolation layer.
10. The control system of claim 9 , wherein measuring the resistance of the resistive memory elements comprises:
measuring a series resistance of the resistive memory elements.
11. The control system of claim 9 , wherein the resistive memory elements are resistive random access memory (ReRAM) elements.