IP Library Granted Patent US 11,699,685
Granted Patent B2
US 11,699,685 · App. 17/375,296 · Granted Jul 11, 2023

Non-cure and cure hybrid film-on-die for embedded controller die

Inventors: Ling Yang (Shanghai, CN); Hui Xu (Shanghai, CN); Chong Un Tan (Shanghai, CN)
Assignee: Western Digital Technologies, Inc.
H01L25/0657H01L24/27H01L24/32H01L24/48H01L24/73H01L2224/27515H01L2224/3201H01L2224/32145H01L2224/48225H01L2224/73215H01L2924/1438
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Quick Facts
Patent No.
US 11,699,685
App. No.
17/375,296
Granted
Jul 11, 2023
Kind
B2
Abstract

A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.

Claims (31)

1. A semiconductor assembly, comprising:

a first die;

a second die;

a film on die (FOD) layer configured to attach the first die to the second die, the FOD layer being disposed on a first surface of the first die and comprising:

a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface; and

a second portion comprising a second DAF disposed on a peripheral region of the first surface surrounding the inner region, the second DAF comprising a different material than the first DAF.

2. The semiconductor assembly of claim 1 , wherein the peripheral region extends from the inner region to one or more edges of the first surface.

3. The semiconductor assembly of claim 2 , wherein the FOD layer does not extend beyond the edges of the first surface.

4. The semiconductor assembly of claim 1 , wherein the first DAF includes a cured DAF, and the second DAF includes a non-cured DAF.

5. The semiconductor assembly of claim 1 , wherein the second die is embedded in the first portion of the FOD layer.

6. The semiconductor assembly of claim 5 , wherein the second die is mounted on a substrate, wherein the second die and the FOD layer are disposed between the substrate and the first die, and wherein the first die and the second die are electrically connected to the substrate.

7. The semiconductor assembly of claim 6 , further comprising one or more bond wires embedded in the first portion of the FOD layer, the one or more bond wires electrically connecting the second die to the substrate.

8. The semiconductor assembly of claim 1 , wherein the first die is a memory die and the second die is a controller die.

9. The semiconductor assembly of claim 8 , wherein the memory die is a NAND die.

10. A method for manufacturing a film on die (FOD), comprising:

forming a first portion of the FOD using a first mask, wherein the first portion comprises a first type of die attach film (DAF), the first mask indicating a size and shape of the first portion;

forming a second portion of the FOD using a second mask, wherein the second portion comprises a second type of DAF, the second mask indicating a size and shape of the second portion; and

assembling the first portion and the second portion to form the FOD, such that the first portion is surrounded by the second portion.

11. The method of claim 10 , wherein the first type of DAF includes a cure type of DAF, and the second type of DAF includes a non-cure type of DAF.

12. The method of claim 10 , wherein the first type of DAF does not include a non-cure type of DAF, and the second type of DAF does not include a cure type of DAF.

13. The method of claim 10 , wherein forming the first portion of the FOD includes forming the first portion of the FOD on a liner, and wherein forming the second portion of the FOD includes forming the second portion of the FOD on another liner.

14. The method of claim 10 , further comprising attaching a dicing tape to a top or bottom surface of the FOD.

15. The method of claim 10 , wherein the first portion is a central portion of the FOD surrounded by the second portion.

16. The method of claim 10 , wherein the first portion has a square or rectangular shape.

17. A semiconductor assembly, comprising:

a first die means for storing data;

a second die means for controlling the first die means;

a film means for attaching the first die means to the second die means, the second die means being embedded in the film means, the film means comprising a first portion and a second portion, wherein the first portion comprises a first type of die attach film (DAF), and the second portion comprises a second type of DAF, wherein the first portion is surrounded by the second portion.

18. The semiconductor assembly of claim 17 , wherein the first portion is a central portion of the film means surrounded by the second portion.

19. The semiconductor assembly of claim 17 , wherein the first type of DAF includes a cure type of DAF, and the second type of DAF includes a non-cure type of DAF.

20. The semiconductor assembly of claim 17 , wherein the first type of DAF does not include a non-cure type of DAF, and the second type of DAF dost not include a cure type of DAF.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: YANG, LING; XU, HUI; TAN, CHONG UN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056863/0340 →