IP Library Granted Patent US 11,204,697
Granted Patent B2
US 11,204,697 · App. 16/827,605 · Granted Dec 21, 2021

Wear leveling in solid state devices

Inventors: Kanishk Rastogi (Maharashtra, IN); Sanoj Kizhakkekara Unnikrishnan (Bangalore, IN); Anand Mitra (Maharashtra, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0608G06F3/064G06F3/0616G06F3/0652G06F3/0658G06F3/0679G06F12/0246G06F2212/1036G06F2212/7205G06F2212/7211
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Quick Facts
Patent No.
US 11,204,697
App. No.
16/827,605
Granted
Dec 21, 2021
Kind
B2
Abstract

Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100-p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.

Claims (45)

1. A storage system, comprising:

a plurality of memory blocks; and

one or more controllers configured to cause:

prior to deleting data from the storage system, determining, for one or more memory blocks of the plurality of memory blocks, whether a wear count value associated with a corresponding memory block of the one or more memory blocks exceeds a wear count threshold; and

in response to determining that the wear count threshold is exceeded for the one or more memory blocks:

determining whether a counter satisfies a threshold number of attempts to identify a memory block associated with a wear count value that does not exceed the wear count threshold; and

when the counter satisfies the threshold number of attempts, selecting a second memory block from the plurality of memory blocks for deleting data from the second memory block.

2. The storage system of claim 1 , wherein the selecting the second memory block comprises selecting randomly the second memory block.

3. The storage system of claim 1 , wherein a wear count value associated with the second memory block does not exceed the wear count threshold.

4. The storage system of claim 1 , wherein the selecting the second memory block comprises selecting the second memory block regardless of the wear count value of the second memory block.

5. The storage system of claim 1 , wherein the one or more controllers are configured to cause:

in response to determining that the wear count threshold is not exceeded for at least one of the one or more memory blocks, deleting data from the at least one of the one or more memory blocks.

6. The storage system of claim 5 , wherein the one or more controllers are configured to cause:

updating the wear count value associated with the at least one of the one or more memory blocks to an updated wear count value.

7. The storage system of claim 6 , wherein the one or more controllers are configured to cause:

identifying, based on the wear count value associated with the at least one of the one or more memory blocks, a first wear count element in a data structure;

identifying, based on the updated wear count value, a second wear count element in the data structure;

determining whether the first wear count element and the second wear count element are different; and

in response to determining that the first wear count element and the second wear count element are different, updating, based on the updated wear count value, the data structure.

8. The storage system of claim 7 , wherein the first wear count element is associated with a first range of wear count values and a first number of memory blocks among the plurality of memory blocks, and wherein the second wear count element is associated with a second range of wear count values and a second number of memory blocks among the plurality of memory blocks of the storage system.

9. The storage system of claim 8 , wherein the one or more controllers are configured to cause:

updating the data structure by decreasing the first number of memory blocks associated with the first wear count element, and increasing the second number of memory blocks associated with the second wear count element.

10. The storage system of claim 8 , wherein the wear count value, associated with the at least one of the one or more memory blocks, is within the first range of wear count values, and wherein the updated wear count value is within the second range of wear count values.

11. A method, comprising:

prior to deleting data from a storage system, determining, for one or more memory blocks of a plurality of memory blocks, whether a wear count value associated with a corresponding memory block of the one or more memory blocks exceeds a wear count threshold; and

in response to determining that the wear count threshold is exceeded for the one or more memory block:

determining whether a counter satisfies a threshold number of attempts to identify a memory block associated with a wear count value that does not exceed the wear count threshold; and

when the counter satisfies the threshold number of attempts, selecting a second memory block from the plurality of memory blocks for deleting data from the second memory block.

12. The method of claim 11 , wherein the selecting the second memory block comprises selecting randomly the second memory block.

13. The method of claim 11 , wherein a wear count value associated with the second memory block does not exceed the wear count threshold.

14. The method of claim 11 , wherein the selecting the second memory block comprises selecting the second memory block regardless of the wear count value of the second memory block.

15. The method of claim 11 , comprising:

in response to determining that the wear count threshold is not exceeded for at least one of the one or more memory blocks, deleting data from the at least one of the one or more memory blocks;

updating the wear count value associated with the at least one of the one or more memory blocks to an updated wear count value;

identifying, based on the wear count value associated with the at least one of the one or more memory blocks, a first wear count element in a data structure;

identifying, based on the updated wear count value, a second wear count element in the data structure;

determining whether the first wear count element and the second wear count element are different; and

in response to determining that the first wear count element and the second wear count element are different, updating, based on the updated wear count value, the data structure.

16. An apparatus, comprising:

prior to deleting data from a storage system, means for determining, for one or more memory blocks of a plurality of memory blocks, whether a wear count value associated with a corresponding memory block of the one or more memory blocks exceeds a wear count threshold; and

in response to determining that the wear count threshold is exceeded for the one or more memory blocks:

means for determining whether a counter satisfies a threshold number of attempts to identify a memory block associated with a wear count value that does not exceed the wear count threshold; and

when the counter satisfies the threshold number of attempts, means for selecting a second memory block from the plurality of memory blocks for deleting data from the second memory block.

17. The apparatus of claim 16 , wherein the means for selecting the second memory block comprises means for selecting randomly the second memory block.

18. The apparatus of claim 16 , wherein a wear count value associated with the second memory block does not exceed the wear count threshold.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2020
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052386/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2020
From: MITRA, ANAND; RASTOGI, KANISHK; UNNIKRISHNAN, SANOJ KIZHAKKEKARA
To: HGST NETHERLANDS B.V.
Reel/Frame 052383/0742 →
Continuity (4)
Continuation 16011572 · Jun 18, 2018
Continuation 15130320 · Apr 15, 2016
Continuation 14509400 · Oct 8, 2014
Related Publication 20200225850A1 · Jul 16, 2020