IP Library Granted Patent US 10,937,510
Granted Patent B2
US 10,937,510 · App. 16/456,522 · Granted Mar 2, 2021

Multidimensional pseudorandom binary sequence analysis for a memory device

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Quick Facts
Patent No.
US 10,937,510
App. No.
16/456,522
Filed
Jun 28, 2019
Granted
Mar 2, 2021
Kind
B2
Art Unit
2827
USPC
365/185.24
Abstract

A method for identifying cell coupling in a memory system includes generating a two-dimensional pseudorandom binary sequence array. The method also includes performing an erase operation on a plurality of cells of a memory block of the memory system. The method also includes performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array. The method also includes performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells. The method also includes identifying cell coupling between respective cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.

Claims (40)

1. A method for identifying cell coupling in a memory system, the method comprising:

generating a two-dimensional pseudorandom binary sequence array that comprises columns and rows;

performing an erase operation on a plurality of cells of a memory block of the memory system;

performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array;

performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells; and

identifying cell coupling between at least two cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.

2. The method of claim 1 , wherein the two-dimensional pseudorandom binary sequence array is a square array including sides of length (2 N −1), wherein N is a polynomial degree.

3. The method of claim 1 , wherein each column and each row of the two-dimensional pseudorandom binary sequence array includes all possible values of the two-dimensional pseudorandom binary sequence array only once.

4. The method of claim 1 , wherein identifying cell coupling between at least two cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells includes identifying a location for each identified cell coupling.

5. The method of claim 1 , wherein identifying cell coupling between at least two cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells includes identifying a magnitude for each identified cell coupling.

6. The method of claim 1 , wherein the plurality of cells are multi-level cells.

7. The method of claim 1 , wherein some of the identified cell couplings include linear cell couplings.

8. The method of claim 1 , wherein some of the identified cell couplings include non-linear cell couplings.

9. A controller comprising:

a bus interface in communication with one or more memory blocks of a memory system; and

a processor configured to:

receive a two-dimensional pseudorandom binary sequence array that comprises columns and rows;

perform an erase operation on a plurality of cells of a memory block of the one or more memory blocks;

perform a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array;

perform a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells; and

identify cell coupling between at least two cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.

10. The controller of claim 9 , wherein the two-dimensional pseudorandom binary sequence array is a square array including sides of length (2 N −1), wherein N is a polynomial degree.

11. The controller of claim 9 , wherein each column and each row of the two-dimensional pseudorandom binary sequence array includes all possible values of the two-dimensional pseudorandom binary sequence array only once.

12. The controller of claim 9 , wherein the processor is further configured to identify a location for each identified cell coupling.

13. The controller of claim 9 , wherein the processor is further configured to identify a magnitude for each identified cell coupling.

14. The controller of claim 9 , wherein the plurality of cells are multi-level cells.

15. The controller of claim 9 , wherein some of the identified cell couplings include linear cell couplings.

16. The controller of claim 9 , wherein some of the identified cell couplings include non-linear cell couplings.

17. A system for identifying cell coupling in a memory system, the system comprising:

at least one memory block; and

a controller in communication with the at least one memory block, the controller including:

a pseudorandom binary sequence generator configured to generates a two-dimensional pseudorandom binary sequence array that comprises columns and rows; and

a cell coupling detector configured to:

perform an erase operation on a plurality of cells of the at least one memory block;

perform a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array;

perform a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells; and

identify cell coupling between at least two cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.

18. The system of claim 17 , wherein the two-dimensional pseudorandom binary sequence array is a square array including sides of length (2 N −1), wherein N is a polynomial degree.

19. The system of claim 17 , wherein each column and each row of the two-dimensional pseudorandom binary sequence array includes all possible values of the two-dimensional pseudorandom binary sequence array only once.

20. The system of claim 17 , wherein the plurality of cells are multi-level cells.

Assignments (7)
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2019
From: GALBRAITH, RICHARD; GOODE, JONAS; YIP, HENRY; KUMAR, RAVI; RAVINDRAN, NIRANJAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049831/0778 →