Granted Patent B2

US 11,488,673 · App. 16/752,516 · Granted Nov 1, 2022

Inventors: Seyhan Karakulak (San Diego, CA); Anthony Dwayne Weathers (San Diego, CA); Richard David Barndt (San Diego, CA)

Assignee: Western Digital Technologies, Inc.

G11C16/26G06F11/073G06F11/076G11C11/5642G11C16/3427G11C16/3495

Abstract

Claims (86)

1. A data storage system, comprising:

a memory comprising a plurality of memory cells, wherein the plurality of memory cells comprise first memory cells and second memory cells, wherein the second memory cells are adjacent to the first memory cells; and

a controller configured to cause:

determining offset memory groups, each paired with an associated offset value to be used for reading memory cells within a corresponding offset memory group,

performing read operations on the second memory cells, wherein the read operations comprise reading the second memory cells multiple times using different read level voltages, each of the different read level voltages being associated with a respective offset value;

generating a plurality of reliability values based on the read operations;

determining a new offset value associated with a zero crossing point in a range of the plurality of reliability values; and

reading the first memory cells using a new read level voltage obtained based on the new offset value,

wherein determining the offset memory groups comprises:

dividing the memory into multiple candidate groups;

selecting a first set of groups from the multiple candidate groups;

generating permutations of subgroups from the first set of groups, each permutation comprising at least two subgroups, each subgroup comprising multiple memory cells;

for each permutation, determining read error counts of each subgroup using offset values;

selecting a permutation having lowest total read error counts; and

selecting one of the subgroups within the selected permutation as a first one of the offset memory groups and the associated offset value, and

wherein the first one of the offset memory groups comprises the second memory cells.

2. The data storage system of claim 1 , wherein the controller is configured to cause determining the zero crossing point based on an interpolation of the plurality of reliability values.

3. The data storage system of claim 2 , wherein the respective offset value is one of a plurality of predetermined offset values, wherein the new offset value is an interpolated offset value, wherein the determining the new offset value comprises interpolating the interpolated offset value between at least two predetermined offset values of the plurality of predetermined offset values, and wherein the interpolated offset value is neither of the at least two predetermined offset values.

4. The data storage system of claim 1 , wherein the controller is configured to cause:

storing a plurality of predetermined offset values, each predetermined offset value being associated with a group of wordlines in the memory for use with a read level voltage in reading memory cells in the group of wordlines; and

for a respective group of wordlines:

updating a read level offset previously stored to the new offset value;

setting a respective read level voltage based on the updated read level offset; and

reading the respective group of wordlines using the respective read level voltage.

5. The data storage system of claim 1 , wherein the first memory cells comprises a first wordline, and the second memory cells comprises a second wordline different from the first wordline.

6. The data storage system of claim 1 , wherein the first memory cells comprises a first codeword, and the second memory cells comprises a second codeword different from the first codeword.

7. The data storage system of claim 1 , wherein the reading the first memory cells using the new read level voltage obtained based on the new offset value comprises reading the first memory cells using the new read level voltage across a plurality of memory channels, wherein each memory channel is configured to address one or more memory blocks of the memory.

8. The data storage system of claim 7 , wherein the reading the first memory cells using the new read level voltage across the plurality of memory channels comprises:

associating the new offset value with all blocks and all pages in the memory that are addressable by the plurality of memory channels; and

using the new read level voltage when reading memory cells of any page or block associated with the plurality of memory channels.

9. The data storage system of claim 1 , wherein the reading the first memory cells using the new read level voltage obtained based on the new offset value comprises:

associating the new offset value with a page address of the memory; and

using the new read level voltage when reading memory cells associated with the page address via any of a plurality of memory channels, each page address addressable via the plurality of memory channels of the memory.

10. The data storage system of claim 1 , wherein each of the plurality of reliability values is indicative of a likelihood that an output state of a memory cell read is equal to one of multiple predetermined programmed states.

11. A machine-implemented method, comprising:

determining offset memory groups within a memory, each offset memory group paired with an associated offset value to be used for reading memory cells within a corresponding offset memory group;

performing read operations on second memory cells that are adjacent to first memory cells, wherein the read operations comprise reading the second memory cells multiple times using different read level voltages, each of the different read level voltages being associated with a respective offset value;

generating a plurality of reliability values based on the read operations;

determining a new offset value associated with a zero crossing point in a range of the plurality of reliability values; and

reading the first memory cells using a new read level voltage obtained based on the new offset value,

wherein determining the offset memory groups comprises:

dividing the memory into multiple candidate groups;

selecting a first set of groups from the multiple candidate groups;

generating permutations of subgroups from the first set of groups, each permutation comprising at least two subgroups, each subgroup comprising multiple memory cells;

for each permutation, determining read error counts of each subgroup using offset values;

selecting a permutation having lowest total read error counts; and

selecting one of the subgroups within the selected permutation as a first one of the offset memory groups and the associated offset value, and

wherein the first one of the offset memory groups comprises the second memory cells.

12. The machine-implemented method of claim 11 , wherein the zero crossing point is determined based on an interpolation of the plurality of reliability values.

13. The machine-implemented method of claim 11 , wherein the respective offset value is one of a plurality of predetermined offset values, wherein the new offset value is an interpolated offset value, wherein the determining the new offset value comprises interpolating the interpolated offset value between at least two predetermined offset values of the plurality of predetermined offset values, and wherein the interpolated offset value is neither of the at least two predetermined offset values.

14. The machine-implemented method of claim 11 , wherein the memory comprises the first memory cells and the second memory cells, and wherein the machine-implemented method comprises:

storing a plurality of predetermined offset values, each predetermined offset value being associated with a group of wordlines in the memory for use with a read level voltage in reading memory cells in the group of wordlines; and

for a respective group of wordlines:

updating a read level offset previously stored to the new offset value;

setting a respective read level voltage based on the updated read level offset; and

reading the respective group of wordlines using the respective read level voltage.

15. A data storage system, comprising:

a memory comprising a plurality of memory cells, wherein the plurality of memory cells comprise first memory cells and second memory cells, wherein the second memory cells are adjacent to the first memory cells;

means for determining offset memory groups, each paired with an associated offset value to be used for reading memory cells within a corresponding offset memory group;

means for performing read operations on the second memory cells, wherein the read operations comprise reading the second memory cells multiple times using different read level voltages, each of the different read level voltages being associated with a respective offset value;

means for generating a plurality of reliability values based on the read operations;

means for determining a new offset value associated with a zero crossing point in a range of the plurality of reliability values; and

means for reading the first memory cells using a new read level voltage obtained based on the new offset value,

wherein the means for determining the offset memory groups comprises:

means for dividing the memory into multiple candidate groups;

means for selecting a first set of groups from the multiple candidate groups;

means for generating permutations of subgroups from the first set of groups, each permutation comprising at least two subgroups, each subgroup comprising multiple memory cells;

for each permutation, means for determining read error counts of each subgroup using offset values;

means for selecting a permutation having lowest total read error counts; and

means for selecting one of the subgroups within the selected permutation as a first one of the offset memory groups and the associated offset value, and

wherein the first one of the offset memory groups comprises the second memory cells.

16. The data storage system of claim 1 , wherein determining the offset memory groups further comprises:

determining a second one of the offset memory groups, based on another one of the subgroups within the selected permutation and a next group from the multiple candidate groups.

17. The data storage system of claim 16 , wherein determining the second one of the offset memory groups comprises:

as a next set of groups, selecting the another one of the subgroups within the selected permutation and the next group from the multiple candidate groups;

generating a second plurality of permutations of subgroups from the next set of groups;

for each of the second plurality of permutations, determining read error counts of each subgroup using offset values;

selecting a second permutation having lowest total read error counts from the second plurality of permutations; and

selecting one of the subgroups within the selected second permutation as the second one of the offset memory groups and the associated offset value.

18. The data storage system of claim 1 , wherein:

dividing the memory into the multiple candidate groups represent boundaries of the multiple candidate groups; and

the multiple candidate groups are consecutive.

19. The data storage system of claim 1 , wherein each subgroup of the permutations comprises consecutive wordlines.

20. The data storage system of claim 1 , wherein the controller is configured to cause:

storing the associated offset value of the first one of the offset memory groups; and

after the new offset value is determined, replacing the associated offset value of the first one of the offset memory groups with the new offset value.

Assignments (11)

Continuity (3)